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MC10161FN

Description
Binary to 1-8 Decoder (Low)
Categorylogic    logic   
File Size119KB,8 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Download Datasheet Parametric Compare View All

MC10161FN Overview

Binary to 1-8 Decoder (Low)

MC10161FN Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQLCC
package instructionQCCJ, LDCC20,.4SQ
Contacts20
Reach Compliance Code_compli
ECCN codeEAR99
Is SamacsysN
series10K
Input adjustmentSTANDARD
JESD-30 codeS-PQCC-J20
JESD-609 codee0
length8.965 mm
Logic integrated circuit typeOTHER DECODER/DRIVER
Humidity sensitivity level1
Number of functions1
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-30 °C
Output characteristicsOPEN-EMITTER
Output polarityINVERTED
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC20,.4SQ
Package shapeSQUARE
Package formCHIP CARRIER
power supply-5.2 V
Maximum supply current (ICC)84 mA
Prop。Delay @ Nom-Su6.4 ns
propagation delay (tpd)6 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
width8.965 mm
Base Number Matches1
MC10161
Binary to 1-8 Decoder
(Low)
The MC10161 is designed to decode a three bit input word to a one
of eight line output. The selected output will be low while all other
outputs will be high. The enable inputs, when either or both are high,
force all outputs high.
The MC10161 is a true parallel decoder. No series gating is used
internally, eliminating unequal delay times found in other decoders.
This design provides the identical 4 ns delay from any address or enable
input to any output.
A complete mux/demux operation on 16 bits for data distribution is
illustrated in Figure 1. This system, using the MC10136 control
counters, has the capability of incrementing, decrementing or holding
data channels. When both S0 and S1 are low, the index counters reset,
thus initializing both the mux and demux units. The four binary
outputs of the counter are buffered by the MC10161s to send
twisted–pair select data to the multiplexer/demultiplexer to units.
P
D
= 315 mW typ/pkg (No Load)
t
pd
= 4.0 ns typ
t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
E0 2
E1 15
6 Q0
5 Q1
4 Q2
3 Q3
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
PDIP–16
P SUFFIX
CASE 648
1
1
PLCC–20
FN SUFFIX
CASE 775
10161
AWLYYWW
MC10161P
AWLYYWW
MC10161L
AWLYYWW
A 7
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
13 Q4
B 9
12 Q5
11 Q6
C 14
10 Q7
V
CC1
E0
Q3
Q2
Q1
Q0
A
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
E1
C
Q4
Q5
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
Q6
Q7
B
TRUTH TABLE
ENABLE
INPUTS
E1
L
L
L
L
L
L
L
L
H
X
E0
L
L
L
L
L
L
L
L
X
H
C
L
L
L
L
H
H
H
H
X
X
INPUTS
B
L
L
H
H
L
L
H
H
X
X
A
L
H
L
H
L
H
L
H
X
X
Q0
L
H
H
H
H
H
H
H
H
H
Q1
H
L
H
H
H
H
H
H
H
H
Q2
H
H
L
H
H
H
H
H
H
H
OUTPUTS
Q3
H
H
H
L
H
H
H
H
H
H
Q4
H
H
H
H
L
H
H
H
H
H
Q5
H
H
H
H
H
L
H
H
H
H
Q6
H
H
H
H
H
H
L
H
H
H
Q7
H
H
H
H
H
H
H
L
H
H
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
MC10161L
MC10161P
MC10161FN
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10161/D

MC10161FN Related Products

MC10161FN MC10161 MC10161P MC10161_02 MC10161L
Description Binary to 1-8 Decoder (Low) Binary to 1-8 Decoder (Low) Binary to 1-8 Decoder (Low) Binary to 1-8 Decoder (Low) Binary to 1-8 Decoder (Low)
Is it Rohs certified? incompatible - incompatible - incompatible
Parts packaging code QLCC - DIP - DIP
package instruction QCCJ, LDCC20,.4SQ - DIP, DIP16,.3 - DIP-16
Contacts 20 - 16 - 16
Reach Compliance Code _compli - _compli - _compli
ECCN code EAR99 - EAR99 - EAR99
series 10K - 10K - 10K
Input adjustment STANDARD - STANDARD - STANDARD
JESD-30 code S-PQCC-J20 - R-PDIP-T16 - R-GDIP-T16
JESD-609 code e0 - e0 - e0
length 8.965 mm - 19.175 mm - 19.49 mm
Logic integrated circuit type OTHER DECODER/DRIVER - OTHER DECODER/DRIVER - OTHER DECODER/DRIVER
Number of functions 1 - 1 - 1
Number of terminals 20 - 16 - 16
Maximum operating temperature 85 °C - 85 °C - 85 °C
Minimum operating temperature -30 °C - -30 °C - -30 °C
Output characteristics OPEN-EMITTER - OPEN-EMITTER - OPEN-EMITTER
Output polarity INVERTED - INVERTED - INVERTED
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY - CERAMIC, GLASS-SEALED
encapsulated code QCCJ - DIP - DIP
Encapsulate equivalent code LDCC20,.4SQ - DIP16,.3 - DIP16,.3
Package shape SQUARE - RECTANGULAR - RECTANGULAR
Package form CHIP CARRIER - IN-LINE - IN-LINE
power supply -5.2 V - -5.2 V - -5.2 V
Maximum supply current (ICC) 84 mA - 84 mA - 84 mA
Prop。Delay @ Nom-Su 6.4 ns - 6.4 ns - 6.4 ns
propagation delay (tpd) 6 ns - 6 ns - 6 ns
Certification status Not Qualified - Not Qualified - Not Qualified
Maximum seat height 4.57 mm - 4.44 mm - 5.08 mm
surface mount YES - NO - NO
technology ECL - ECL - ECL
Temperature level OTHER - OTHER - OTHER
Terminal surface Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb)
Terminal form J BEND - THROUGH-HOLE - THROUGH-HOLE
Terminal pitch 1.27 mm - 2.54 mm - 2.54 mm
Terminal location QUAD - DUAL - DUAL
width 8.965 mm - 7.62 mm - 7.62 mm
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