PTLV9352IPWR datasheet, PDF - EEWORLD Datasheet

PTLV9352IPWR: Description40-V, dual 3.5MHz, RRO, MUX-friendly operational amplifier for cost-sensitive systems 8-TSSOP -40 to 125; CategoryAnalog mixed-signal IC Amplifier circuit; File Size3MB，45 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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PTLV9352IPWR Overview

40-V, dual 3.5MHz, RRO, MUX-friendly operational amplifier for cost-sensitive systems 8-TSSOP -40 to 125

Parameter Name	Attribute value
Brand Name	Texas Instruments
Maker	Texas Instruments
package instruction	TSSOP,
Reach Compliance Code	unknown
Amplifier type	OPERATIONAL AMPLIFIER
Minimum Common Mode Rejection Ratio	95 dB
Nominal Common Mode Rejection Ratio	110 dB
Maximum input offset voltage	2000 µV
JESD-30 code	R-PDSO-G8
length	4.4 mm
Negative supply voltage upper limit	-21 V
Number of functions	2
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Maximum seat height	1.2 mm
Nominal slew rate	20 V/us
Maximum slew rate	1.6 mA
Supply voltage upper limit	21 V
surface mount	YES
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Nominal Uniform Gain Bandwidth	3500 kHz
width	3 mm

	PTLV9352IPWR	PTLV9352IDR	TLV9352	TLV9352IDR	TLV9352IPWR
Description	40-V, dual 3.5MHz, RRO, MUX-friendly operational amplifier for cost-sensitive systems 8-TSSOP -40 to 125	40-V, dual 3.5MHz, RRO, MUX-friendly operational amplifier for cost-sensitive systems 8-SOIC -40 to 125	40-V, dual 3.5MHz, RRO, MUX-friendly operational amplifier for cost-sensitive systems 8-SOIC -40 to 125	40-V, dual 3.5MHz, RRO, MUX-friendly operational amplifier for cost-sensitive systems 8-SOIC -40 to 125	40-V, dual 3.5MHz, RRO, MUX-friendly operational amplifier for cost-sensitive systems 8-TSSOP -40 to 125
CMRR(Min)(dB)	-	-	95	95	95
Features	-	-	Cost Optimized,EMI Hardened	Cost Optimized,EMI Hardened	Cost Optimized,EMI Hardened
Input bias current(Typ)(pA)	-	-	10	10	10
Rail-to-rail	-	-	In to V-,Out	In to V-,Out	In to V-,Out
Rating	-	-	Catalog	Catalog	Catalog
Slew rate(Typ)(V/us)	-	-	20	20	20
GBW(Typ)(MHz)	-	-	3.5	3.5	3.5
Iq per channel(Max)(mA)	-	-	0.8	0.8	0.8
Iq per channel(Typ)(mA)	-	-	0.65	0.65	0.65
Package Group	-	-	SOIC\|8,TSSOP\|8	SOIC\|8,TSSOP\|8	SOIC\|8,TSSOP\|8
Total supply voltage(Min)(+5V=5, +/-5V=10)	-	-	4.5	4.5	4.5
Total supply voltage(Max)(+5V=5, +/-5V=10)	-	-	40	40	40
Architecture	-	-	CMOS	CMOS	CMOS
Vos (offset voltage @ 25 C)(Max)(mV)	-	-	1.8	1.8	1.8
Output current(Typ)(mA)	-	-	60	60	60
Number of channels(#)	-	-	2	2	2
CMRR(Typ)(dB)	-	-	110	110	110
Offset drift(Typ)(uV/C)	-	-	1.5	1.5	1.5
Operating temperature range(C)	-	-	-40 to 125	-40 to 125	-40 to 125
Vn at 1 kHz(Typ)(nV/rtHz)	-	-	15	15	15
Approx. price(US$)	-	-	0.37 \| 1ku	0.37 \| 1ku	0.37 \| 1ku

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