74FCT162511CTPAG8 datasheet, PDF

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74FCT162511CTPAG8: DescriptionTSSOP-56, Reel; Categorylogic; File Size237KB，11 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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74FCT162511CTPAG8 Overview

TSSOP-56, Reel

74FCT162511CTPAG8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	GREEN, TSSOP-56
Contacts	56
Manufacturer packaging code	PAG56
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
Control type	INDEPENDENT CONTROL
Counting direction	BIDIRECTIONAL
series	FCT
JESD-30 code	R-PDSO-G56
JESD-609 code	e3
length	14 mm
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
MaximumI(ol)	0.064 A
Humidity sensitivity level	1
Number of digits	16
Number of functions	1
Number of ports	2
Number of terminals	56
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP56,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Prop。Delay @ Nom-Sup	4.2 ns
propagation delay (tpd)	5.3 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
translate	N/A
Trigger type	POSITIVE EDGE
width	6.1 mm
Base Number Matches	1

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IDT54/74FCT162511AT/CT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER

MILITARY AND INDUSTRIAL TEMPERATURE RANGES

FAST CMOS 16-BIT

IDT54/74FCT162511AT/CT

REGISTERED/LATCHED

TRANSCEIVER WITH PARITY

FEATURES:

•

0.5 MICRON CMOS Technology

Typical t

sk(o)

(Output Skew) < 250ps, clocked mode

Low input and output leakage

≤

1µA (max)

ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

= 5V ±10%

Balanced Output Drivers:

– ±24mA (industrial)

– ±16mA (military)

Series current limiting resistors

Generate/Check, Check/Check modes

Open drain parity error allows wire-OR

Available in the following packages:

– Industrial: SSOP, TSSOP

– Military: CERPACK

DESCRIPTION:

The FCT162511T 16-bit registered/latched transceiver with parity is built

using advanced dual metal CMOS technology. This high-speed, low-power

transceiver combines D-type latches and D-type flip-flops to allow data flow in

transparent, latched, or clocked modes. The device has a parity generator/

checker in the A-to-B direction and a parity checker in the B-to-A direction. Error

checking is done at the byte level with separate parity bits for each byte. Separate

error flags exits for each direction with a single error flag indicating an error for

either byte in the A-to-B direction and a second error flag indicating an error for

either byte in the B-to-A direction. The parity error flags are open drain outputs

which can be tied together and/or tied with flags from other devices to form a single

error flag or interrupt. The parity error flags are enabled by the

OExx

control

pins allowing the designer to disable the error flag during combinational

transitions.

The control pins LEAB, CLKAB, and

OEAB

control operation in the A-to-B

direction while LEBA, CLKBA, and

OEBA

control the B-to-A direction.

GEN/

CHK is only for the selection of A-to-B operation. The B-to-A direction is always

in checking mode. The ODD/EVEN select is common between the two directions.

Except for the ODD/EVEN control, independent operation can be achieved

between the two directions by using the corresponding control lines.

•

FUNCTIONAL BLOCK DIAGRAM

LEAB

CLKAB

Data

Parity

GEN/CHK

Byte

Parity

Generator/

Checker

Latch/

Parity, data

OEAB

B0-15

PB1,2

PERB

(Open Drain)

A0-15

PA1,2

ODD/EVEN

LEBA

CLKBA

Parity, data

OEBA

PERA

(Open Drain)

Latch/

Byte

Parity

Checking

Parity, Data

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND INDUSTRIAL TEMPERATURE RANGES

SEPTEMBER 2009

DSC-2916/4

74FCT162511CTPAG8 Related Products

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Description	TSSOP-56, Reel	SSOP-56, Tube	SSOP-56, Reel	SSOP-56, Tube	TSSOP-56, Tube	TSSOP-56, Reel	TSSOP-56, Tube
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TSSOP	SSOP	SSOP	SSOP	TSSOP	TSSOP	TSSOP
package instruction	GREEN, TSSOP-56	SOP, SSOP56,.4	SSOP-56	SOP, SSOP56,.4	SOP, TSSOP56,.3,20	GREEN, TSSOP-56	SOP, TSSOP56,.3,20
Contacts	56	56	56	56	56	56	56
Manufacturer packaging code	PAG56	PVG56	PVG56	PVG56	PAG56	PAG56	PAG56
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Control type	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL
Counting direction	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL
series	FCT	FCT	FCT	FCT	FCT	FCT	FCT
JESD-30 code	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56
JESD-609 code	e3	e3	e3	e3	e3	e3	e3
length	14 mm	18.415 mm	18.415 mm	18.415 mm	14 mm	14 mm	14 mm
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
MaximumI(ol)	0.064 A	0.064 A	0.064 A	0.064 A	0.064 A	0.064 A	0.064 A
Humidity sensitivity level	1	1	1	1	1	1	1
Number of digits	16	16	16	16	16	16	16
Number of functions	1	1	1	1	1	1	1
Number of ports	2	2	2	2	2	2	2
Number of terminals	56	56	56	56	56	56	56
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE WITH SERIES RESISTOR	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SOP	SSOP	SOP	SOP	TSSOP	SOP
Encapsulate equivalent code	TSSOP56,.3,20	SSOP56,.4	SSOP56,.4	SSOP56,.4	TSSOP56,.3,20	TSSOP56,.3,20	TSSOP56,.3,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
method of packing	TAPE AND REEL	TUBE	TAPE AND REEL	TUBE	TUBE	TAPE AND REEL	TUBE
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Prop。Delay @ Nom-Sup	4.2 ns	5 ns	4.2 ns	4.2 ns	5 ns	5 ns	4.2 ns
propagation delay (tpd)	5.3 ns	5.6 ns	5.3 ns	5.3 ns	5.6 ns	5.6 ns	5.3 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	2.794 mm	2.794 mm	2.794 mm	1.1 mm	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.635 mm	0.635 mm	0.635 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30	30	30
translate	N/A	N/A	N/A	N/A	N/A	N/A	N/A
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	6.1 mm	7.493 mm	7.5 mm	7.493 mm	6.1 mm	6.1 mm	6.1 mm

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