AD9531BCPZ datasheet, PDF - EEWORLD Datasheet

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AD9531BCPZ: DescriptionIC CLK GEN PLL 400MHK 88LFCSP; Categorysemiconductor Analog mixed-signal IC; File Size1MB，88 Pages; ManufacturerADI; Websitehttps://www.analog.com; Environmental Compliance

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AD9531BCPZ Overview

IC CLK GEN PLL 400MHK 88LFCSP

AD9531BCPZ Parametric

Parameter Name	Attribute value
PLL	yes
enter	CMOS, LVDS, LVPECL, crystal
output	CMOS，HSTL，LVDS
Number of circuits	3
Ratio - Input:Output	2:10，1:12，1:2
Differential - Input:Output	Yes Yes
Frequency - maximum	400MHz
Frequency divider/multiplier	Yes Yes
Voltage - Power	1.71 V ~ 3.465 V
Operating temperature	-40°C ~ 85°C
Installation type	surface mount
Package/casing	88-VFQFN Exposed Pad, CSP
Supplier device packaging	88-LFCSP-VQ（12x12）

User Manual

【User Guides】UG-945: Evaluation Board for 16-Lead TSSOP Devices in the Switches and Multiplexers Portfolio (Rev. 0)

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Data Sheet

FEATURES

3-Channel Clock Generator, 24 Outputs

AD9531

GENERAL DESCRIPTION

The

AD9531

provides a multioutput clock generator function

and three on-chip phase-locked loop (PLL) cores with SPI

programmable output frequencies and formats.

PLL1 provides two reference inputs and 10 outputs and includes

four user selectable loop configurations. The PLL has a fully

integrated loop filter requiring only a single external capacitor

(or a series RC network). PLL1 provides a wide range of output

frequencies up to 400 MHz and is capable of operating with an

external voltage controlled crystal oscillator (VCXO) and loop

filter, instead of the integrated voltage controlled oscillator

(VCO) and loop filter.

PLL2 is an integer-N PLL providing a single reference input and

12 outputs. PLL2 synthesizes output frequencies up to 400 MHz

from the REF2_x source and synchronizes the output clocks to

the input reference.

PLL3 provides a single reference input and two outputs. PLL3

synthesizes output frequencies up to 400 MHz from the REF3_x

source and synchronizes the output clocks to input reference.

The

AD9531

is available in an 88-lead LFCSP and is specified

over the −40°C to +85°C operating temperature range.

Throughout this data sheet, multifunction pins, such as

LOR/M4, are referred to either by the entire pin name or by a

single function of the pin (for example, LOR, when only that

function is relevant). In other cases, the text and figures of this

data sheet contain references to a channel rather than a pin. For

example, REF_A refers to the REF_A channel rather than the

REF_AP and REF_AN pins. Likewise, OUT3_1 refers to

Channel 1 of PLL3 rather than the OUT3_1P and OUT3_1N pins.

Additionally, an abbreviated notation for a pin pair replaces an

explicit reference to a each pin (for example, REF_Ax signifies

the REF_AN and REF_AP pins.).

3 fully integrated PLL/VCO cores (PLL1, PLL2, and PLL3)

Jitter performance: 0.462 ps rms typical

PLL1, fractional-N mode, 12 kHz to 20 MHz bandwidth

Loss of reference and lock detection for each PLL

Pin-configurable common frequency translations

Automatic synchronization of all outputs on power-up

Manual output synchronization capability

Package available in an 88-lead LFCSP

PLL1 details

Fractional-N/integer-N modes

Optional external VCXO

Fixed delay mode for constant static phase offset

2 reference clock inputs

Input format: differential/single-ended

Frequency range: 9.5 MHz to 260 MHz

Reference switching: manual/automatic

10 ultralow jitter HSTL/CMOS outputs up to 400 MHz

PLL2 details

Integer-N mode (1 reference clock input)

Input format: differential/single-ended/crystal

Frequency range: 9.5 MHz to 250 MHz

12 HSTL/CMOS outputs up to 400 MHz

PLL3 details

Integer-N mode (1 reference clock input)

Frequency range: 9.5 MHz to 100 MHz

Input format: differential/crystal (supports a 25 MHz to

50 MHz AT-cut quartz crystal resonator)

2 HSTL/LVDS/CMOS outputs to 400 MHz/150 MHz

(differential/CMOS)

APPLICATIONS

Radio equipment controller clocking

Low jitter/phase noise clock generation and distribution

Clock generation and translation for SONET, 10GE, 10G FC,

and other 10 Gbps protocols

40 Gbps/100 Gbps networking line cards, including SONET,

synchronous ethernet, OTU2/3/4

Forward error correction (G.710)

High performance wireless transceivers

ATE and high performance instrumentation

Broadband infrastructures

Ethernet line cards, switches, and routers

SATA and PCI-express

Rev. 0

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

AD9531

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Conditions ..................................................................................... 5

Supply Current .............................................................................. 5

Power Dissipation ......................................................................... 6

LDET1/M1, LDET2/M2, LDET3/M3, and LOR/M4 Pins ...... 8

REF1_SEL Pin ............................................................................... 8

PLL1 Characteristics .................................................................... 8

PLL2 Characteristics .................................................................. 13

PLL3 Characteristics .................................................................. 17

Serial Control Port ..................................................................... 20

Absolute Maximum Ratings .......................................................... 21

ESD Caution ................................................................................ 21

Pin Configuration and Function Descriptions ........................... 22

Typical Performance Characteristics ........................................... 25

PLL1 Characteristics .................................................................. 25

PLL2 Characteristics .................................................................. 26

PLL3 Characteristics .................................................................. 27

General Characteristics ............................................................. 28

Terminology .................................................................................... 29

Theory of Operation ...................................................................... 30

PLL1—Integer/Fractional-N PLL ............................................ 30

PLL1 Loop Configurations........................................................ 31

PLL1 Reference Clock Inputs (REF1_Ax/REF1_Bx)............. 34

PLL1 Reference Frequency Scaling .......................................... 34

PLL1 Phase Frequency Detector (PFD) and Charge Pumps..... 35

PLL1 Loop Filter ......................................................................... 35

PLL1 Internal VCO .................................................................... 35

PLL1 VCO Divider (M1) ........................................................... 35

PLL1 External VCXO Input (RFIN1_x) .................................. 35

PLL1 Clock Distribution ........................................................... 36

PLL1 Holdover Mode and Freerun Mode ............................... 37

PLL1 Reference Selection—Manual and Automatic ............. 37

PLL1 Internal VCO Calibration ............................................... 38

PLL1 Σ-Δ Modulator.................................................................. 40

PLL1 Lock Detector ................................................................... 40

Data Sheet

PLL2—Integer-N PLL ................................................................ 41

PLL2 Reference Clock Input (REF2_P/REF2_N) .................. 41

PLL2 Reference Divider (R2) .................................................... 41

PLL2 PFD and Charge Pump ................................................... 41

PLL2 Loop Filter ......................................................................... 42

PLL2 VCO ................................................................................... 42

PLL2 VCO Divider (M2)........................................................... 44

PLL2 Feedback Divider (N2) .................................................... 44

PLL2 Clock Distribution ........................................................... 44

PLL3 Integer-N PLL ................................................................... 46

PLL3 Reference Clock Input (REF3_P/REF3_N) .................. 46

PLL3 Input Frequency Scaling ................................................. 46

PLL3 PFD and Charge Pumps .................................................. 46

PLL3 Loop Filters ....................................................................... 47

PLL3 VCOs ................................................................................. 47

PLL3 Feedback Dividers ............................................................ 47

PLL3B Reference Divider (R3B) .............................................. 47

PLL3 Clock Distribution ........................................................... 47

Additional Features ........................................................................ 49

Power-On Reset (POR) ............................................................. 49

ROM Profiles .............................................................................. 49

Multifunction Pins (LDET1/M1, LDET2/M2, LDET3/M3,

LOR/M4) ..................................................................................... 49

Loss of Reference (LOR)............................................................ 50

PLL Lock Detection (LDETx) .................................................. 51

Automatic Output Synchronization ........................................ 51

Serial Control Port ......................................................................... 54

Serial Control Port Pin Descriptions ....................................... 54

Operation of the Serial Control Port ....................................... 54

Instruction Word (16 Bits) ........................................................ 55

MSB/LSB First Transfers ........................................................... 55

Serial Port Control Registers—Register 0x0000 to Register

0x0005 .......................................................................................... 60

Device Identification and ROM Profile Registers—Register

0x000A to Register 0x000E ....................................................... 60

Status Registers—Register 0x0080 to Register 0x0082 .......... 61

LDET/LOR Control Registers—Register 0x0083 to Register

0x0085 .......................................................................................... 61

PLL1 Registers ............................................................................ 62

Rev. 0 | Page 2 of 88

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