EEWORLDEEWORLDEEWORLD

Part Number

Search

BU-PB24-9

Description
TEST LEAD BANANA TO BANANA 24"
CategoryTopical application    Test and measurement   
File Size164KB,1 Pages
ManufacturerMueller Electric
Websitehttp://muellerelectric.com/
Environmental Compliance
Download Datasheet Parametric View All

BU-PB24-9 Online Shopping

Suppliers Part Number Price MOQ In stock  
BU-PB24-9 - - View Buy Now

BU-PB24-9 Overview

TEST LEAD BANANA TO BANANA 24"

BU-PB24-9 Parametric

Parameter NameAttribute value
stacking methodMulti-stack, front and vertical stack (two connectors)
Configurationbanana plug to banana plug
first connectorBanana plug, single, stackable
Second connectorBanana plug, single, stackable
cable length24.0"(609.60mm)
typepatch cord
content1 lead, white
Material - InsulationPolyvinyl chloride (PVC)
Wire gauge18 AWG
Voltage - Rated1000V(1kV)
grade-
Rated current15A
 
 
BU‐PB‐XX‐* 
(Test Lead:  Stackable Banana Plugs each end) 
The BU‐PB‐XX‐* is a test lead with stackable, 4mm banana plugs on each 
end.  The banana plugs mate with any standard 4mm banana jack. 
Constructed with 18 AWG PVC jacketed, test lead wire and has color 
matching polypropylene banana over‐molds  
Banana plugs are nickel plated beryllium copper 
Length:  The “XX” in the model number represents the overall length in 
inches.  Standard lengths are: 12” (30cm), 24” (61cm) , 36”(.9m), 48” (1.2m) 
and 60” (1.5m) 
Color:  The “*” in the model number represents color.  Available colors are: 
‐0 Black,  ‐2 Red,  ‐4 Yellow,  ‐5 Green,  ‐6 Blue,  ‐9 White 
Ratings:  Hands free testing to 1000V.,   15 Amps.  
RoHS Compliant 
 
Mueller Electric Company
1208 Massillon Rd. Ste. N-1500
Akron, OH 44306-4524
www.muellerelectric.com
Toll Free: 800.955.2629
Phone: 330.780.2525
Fax: 330.780.2524
 
Intel-FPGA on-chip memory design issues
Intel-FPGA on-chip memory design issues...
郝旭帅 FPGA/CPLD
DSP digital anti-noise module for airborne communication equipment
The third generation of anti-noise products in China currently use dynamic noise reduction (DNR) technology. DNR technology dynamically adjusts the output voice switch through the changing voice peak ...
fish001 DSP and ARM Processors
ESP32-C3 development board for 9.9 yuan with free shipping
I bought an ESP32-C3 development board for 9.9 yuan a few days ago, with free shipping, and planned to try running micropython on it. It is very small and well made....
dcexpert maychang Fun Electronics
Design method of high-speed graphics frame storage using DSP+FPGA architecture
Frame memory is the data channel between the graphics processor and the display device. All the graphic data to be displayed is first stored in the frame memory and then sent out for display. Therefor...
fish001 DSP and ARM Processors
Why can the defined pointer be used as an array?
/*Clear screen function--clear the entire screen to the same color*/void lcd_clear(unsigned int color){unsigned int num;unsigned int i = 0;unsigned int *startaddr = (unsigned int*)tftlcd_dev.framebuff...
shijizai Linux and Android
Have you ever used the YU4215 chip, SMD SO-8 package?
Have you ever used the YU4215 chip, SMD SO-8 package?...
蓝雨夜 Automotive Electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号