IMEC’s analysis of wafer-level packaging

What is IMEC for wafer-level packaging? What does it do? IMEC proposes a new approach to sector-shaped wafer-level packaging that can meet the needs of higher-density, higher-bandwidth chip-to-chip connections. Arnita Podpod, Senior R&D Engineer at IMEC, and Eric Beyne, IMEC Fellow and Program Director of the 3D Systems Integration Program, introduced the technology, discussed the main challenges and value, and listed potential applications.

Wafer Level Packaging: Attractive Packaging Solutions for Mobile Applications

Today, many electronic systems still consist of multiple components that are individually packaged after wafer dicing and interconnected using traditional printed circuit boards. However, over the years, advanced 3D integration and interconnection technologies have been required for more "demanding" applications. Because this significantly reduces the size of electronic systems and enables faster, shorter connections between subcircuits. One of these technologies is Wafer Level Packaging, in which multiple die are packaged simultaneously on a wafer. Since the entire wafer is now packaged in one go, the solution is less expensive than traditional packaging options. In addition, the resulting packaged chip is smaller and thinner, which is highly valued in size-sensitive devices such as smartphones. In today's smartphones, about 5/7 of the chips are wafer-level packaged, and the number is still increasing.

Fan-in and fan-out

There are two main types of wafer-level packaging: fan-in and fan-out, and they differ primarily in the redistribution layer. A redistribution layer (usually an organic layer) is used to reroute the die's interfaces (I/O) to the desired (bump) locations. Fan-in is where the redistribution layer traces are routed inward to create a very small package (roughly corresponding to the size of the die itself). However, the redistribution process can also be used to expand the usable area of ​​the package, extending the chip contacts beyond the chip size to form a fan-out package. Generally, this fan-out WLP (FO-WLP) technology provides a higher number of I/Os than the fan-in WLP technology.

In mobile applications, fan-out wafer-level packaging is gradually replacing more traditional package-on-package (PoP) memory logic chip stacking solutions.

These PoPs are much thicker than fan-out and are limited by interconnect bandwidth and density and limited pitch scaling (a few hundred microns). In these applications, FO-WLP also outperforms other available high-bandwidth 3D technologies, such as 3D stacking (where hot spots in the logic die can impact memory data retention) or 2.5D stacking (where longer interconnect lines create higher interconnect power and additional cost).

Two basic "fan-out" processes

Over the past few years, various FO-WLP approaches have emerged to meet the growing demand for high data rates and wide I/O counts, and to meet the need for increased functional integration on the package. All these methods start with one of two basic fan-out processes: "mold first" or "redistribution layer first".

In the “mold first” process, the die are first assembled on a temporary carrier, followed by wafer overmolding. The function of epoxy is to protect the individual components and glue them together. At the end, make the repartition layer and make the connections. In the "redistribution layer first" process, the redistribution layer process is followed by die assembly and wafer injection molding.

Each of these methods has its own set of disadvantages. For example, in a “mold first” process, the die is often shifted after injection molding, which makes achieving sub-100μm interconnect pitches very challenging. In the “redistribution layer first” process, the achievable density is limited by the linear and spatial resolution that the (organic) redistribution layer can achieve.

Flip-chip on FO-WLP: A new “fan-out” approach enables higher interconnect densities To meet the demand for higher density, higher bandwidth chip-to-chip connections, the IMEC team is working on 300mm wafers A novel FO-WLP method called Flip-chip on FO-WLP was developed. This process is a "mold first" process, but in contrast to the standard "mold first" process, the chips are already connected to each other before overmolding.

The advantages, as well as the challenges, of this approach are explained below.

This new fan-out solution has been verified on TQV. TQV consists of seven independent chip components: Wide I/O DRAM, flash memory, logic, two TPV dies and two silicon bridges. Because this TQV is only used for verification. Therefore, logic and memory chips are not fully functional: they are "analog" die used to test electrical continuity between bump connections.

Silicon bridges and TPV dies are key components for enabling high-density connections. The TPV die features through silicon vias (TSVs) and 40μm pitch bumps. The silicon bridge has bumps with 40μm and 20μm pitch. These elements form a bridge between functional chips such as logic and memory chips, enabling ultra-high chip-to-chip interconnect density with 20μm bump pitch. Another key process is the tight alignment between dies compared to standard “mold first” processes. During this critical assembly step, individual dies need to be placed with high precision and temporarily bonded to a flat silicon wafer.

Process details

In the first step of the assembly process, the TPV wafer and logic die are placed on a carrier wafer covered with a temporary bonding layer. Next, a thermal compression bonding (TCB) process is used to connect the silicon bridge (with 40μm and 20μm bump pitch) to the logic die and TPV die. In this process step, bumps with 40μm pitch are connected to the left side of the logic die and the TPV die. 20μm pitch bumps are attached to the right side of the logic die. In the next step, the wafer is injection molded from the liquid compound. Testing showed complete filling, even of the area under the silicon bridge. The copper pillars are then exposed by grinding and polishing for later connection to the redistribution layer. After the thinned wafer is turned over and the second carrier is bonded, the first carrier is removed. Afterwards, the memory die are assembled using flip-chip technology. Finally, another wafer-level injection molding and removal of the second carrier completes the process flow. Between process steps, continuity testing is performed to verify circuit integrity. The final result is a chip with a package thickness of only 300-400μm (excluding solder balls).

Main challenges and solutions

This process flow creates a set of challenges that need to be overcome to ensure a fully functional packaging solution with ultra-high chip-to-chip interconnect density.

One issue is the potential for the die to tilt during the assembly process, especially with long, narrow TPV dies and silicon bridges. Tilting of these dies can disrupt interconnections between components. To assess if and when tilt occurs, the IMEC team applied different forces to place the TPV die. The team observed that even with maximum placement force, tilt was limited to less than 5 μm, which is low enough to maintain connectivity. Next is the alignment between the logic die and the TPV die, which has attracted considerable attention and is considered a key factor in the FO-WLP process.

The logic die and TPV die are very close to each other and require precise alignment steps to achieve subsequent silicon bridge 40μm and 20μm bump pitch stacking. For example, to achieve the required 20μm bump pitch, only a maximum +/-3μm alignment error between the logic die and the TPV die can be tolerated. To achieve this extremely small error, the team introduced alignment marks into the carrier and die designs. The logic die is first aligned with the carrier. Next, the TPV die is placed, aligned with the carrier and therefore the logic die. Finally, high-precision stacked thermocompression bonding equipment is used to place the silicon bridges.

The die can still shift during the subsequent molding process, damaging the bump connections between the TPV and silicon bridge or between the logic die and silicon bridge. Therefore, the IMEC team conducted specialized electrical testing before and after molding. Testing has shown that the molding process does not affect the integrity of the connection. Based on these results, it can be hypothesized that if the dies shift during injection molding, they should all move in the same direction and thus not disrupt connectivity.

Summary and future outlook

With this novel approach, the IMEC team demonstrated record-breaking chip-to-chip interconnect density with 20μm bump pitch in a fan-out environment. In the near future, the technology will be further improved and the electrical and RF behavior will be evaluated in different configurations.

The proposed technology is particularly attractive for mobile applications as it enables cost-effective WideI/O memory-to-logic chip interconnect in a very small form factor. Eventually, flip-chip on FO-WLP may also become an enabling technology for heterogeneous integration, targeting high-performance applications. It can provide a way to integrate multiple dies, including high-performance computing, memory and optical communications modules, in electrically highly interconnected packages. The above are some thoughts of IMEC on wafer-level packaging. I hope it will be helpful to everyone.