M393B5170FH0-YH9 datasheet, PDF

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M393B5170FH0-YH9: DescriptionDDR DRAM Module, 512MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240; Categorystorage; File Size1MB，49 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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M393B5170FH0-YH9 Overview

DDR DRAM Module, 512MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240

M393B5170FH0-YH9 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	240
Reach Compliance Code	unknown
ECCN code	EAR99
Is Samacsys	N
access mode	DUAL BANK PAGE BURST
Maximum access time	0.255 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N240
length	133.35 mm
memory density	38654705664 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	240
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature
organize	512MX72
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
Maximum seat height	30.15 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.45 V
Minimum supply voltage (Vsup)	1.2825 V
Nominal supply voltage (Vsup)	1.35 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Base Number Matches	1

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Rev. 1.01, Jan. 2010

M393B2873FH0

M393B5673FH0

M393B5670FH0

M393B5173FH0

M393B5170FH0

240pin Registered DIMM

based on 1Gb F-die

1.35V

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ

-1-

Registered DIMM

datasheet

Rev. 1.01

DDR3L SDRAM

Table Of Contents

240pin Registered DIMM based on 1Gb F-die

1. DDR3L Registered DIMM Ordering Information ........................................................................................................... 5

2. Key Features................................................................................................................................................................. 5

3. Address Configuration .................................................................................................................................................. 5

4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................ 6

5. Pin Description ............................................................................................................................................................. 7

6. ON DIMM Thermal Sensor ........................................................................................................................................... 7

7. Input/Output Functional Description.............................................................................................................................. 8

8. Pinout Comparison Based On Module Type................................................................................................................. 9

9. Registering Clock Driver Specification .......................................................................................................................... 10

9.1 Timing & Capacitance values .................................................................................................................................. 10

9.2 Clock driver Characteristics ..................................................................................................................................... 10

10. Function Block Diagram: ............................................................................................................................................. 11

10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... 11

10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................. 12

10.3 2GB, 256Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ................................................................... 13

10.4 4GB, 512Mx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ................................................................. 14

10.5 4GB, 512Mx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) ................................................................. 16

10.6 8GB, 1Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs) ..................................................................... 17

11. Absolute Maximum Ratings ........................................................................................................................................ 22

11.1 Absolute Maximum DC Ratings............................................................................................................................. 22

11.2 DRAM Component Operating Temperature Range .............................................................................................. 22

12. AC & DC Operating Conditions................................................................................................................................... 22

12.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 22

13. AC & DC Input Measurement Levels .......................................................................................................................... 23

13.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 23

13.2 V

REF

Tolerances.................................................................................................................................................... 24

13.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 25

13.3.1. Differential Signals Definition ......................................................................................................................... 25

13.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 25

13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 26

13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 27

13.4 Slew Rate Definition for Single Ended Input Signals ............................................................................................. 27

13.5 Slew rate definition for Differential Input Signals ................................................................................................... 27

14. AC & DC Output Measurement Levels ....................................................................................................................... 28

14.1 Single Ended AC and DC Output Levels............................................................................................................... 28

14.2 Differential AC and DC Output Levels ................................................................................................................... 28

14.3 Single-ended Output Slew Rate ............................................................................................................................ 28

14.4 Differential Output Slew Rate ................................................................................................................................ 29

15. IDD specification definition.......................................................................................................................................... 30

16. IDD SPEC Table ......................................................................................................................................................... 32

17. Input/Output Capacitance ........................................................................................................................................... 35

18. Electrical Characteristics and AC timing ..................................................................................................................... 36

18.1 Refresh Parameters by Device Density................................................................................................................. 36

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 36

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 36

18.3.1. Speed Bin Table Notes .................................................................................................................................. 39

19. Timing Parameters by Speed Grade .......................................................................................................................... 40

19.1 Jitter Notes ............................................................................................................................................................ 43

19.2 Timing Parameter Notes........................................................................................................................................ 44

20. Physical Dimensions................................................................................................................................................... 45

20.1 128Mbx8 based 128Mx72 Module (1 Rank) - M393B2873FH0 ............................................................................ 45

20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs45

-3-

M393B5170FH0-YH9 Related Products

	M393B5170FH0-YH9	M393B5673FH0-YF8	M393B5670FH0-YF8	M393B5173FH0-YH9	M393B5173FH0-YF8	M393B2873FH0-YH9	M393B5170FH0-YF8	M393B5670FH0-YH9	M393B5673FH0-YH9
Description	DDR DRAM Module, 512MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 256MX72, 0.3ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 256MX72, 0.3ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.3ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 128MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.3ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 256MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 256MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
Parts packaging code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,
Contacts	240	240	240	240	240	240	240	240	240
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknow	unknow	unknow	unknow
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	SINGLE BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	SINGLE BANK PAGE BURST	DUAL BANK PAGE BURST	SINGLE BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	0.255 ns	0.3 ns	0.3 ns	0.255 ns	0.3 ns	0.255 ns	0.3 ns	0.255 ns	0.255 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240
length	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm
memory density	38654705664 bit	19327352832 bit	19327352832 bit	38654705664 bit	38654705664 bit	9663676416 bi	38654705664 bi	19327352832 bi	19327352832 bi
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	72	72	72	72	72	72	72	72	72
Number of functions	1	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1	1
Number of terminals	240	240	240	240	240	240	240	240	240
word count	536870912 words	268435456 words	268435456 words	536870912 words	536870912 words	134217728 words	536870912 words	268435456 words	268435456 words
character code	512000000	256000000	256000000	512000000	512000000	128000000	512000000	256000000	256000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C
organize	512MX72	256MX72	256MX72	512MX72	512MX72	128MX72	512MX72	256MX72	256MX72
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	30.15 mm	30.15 mm	30.15 mm	30.15 mm	30.15 mm	30.15 mm	30.15 mm	30.15 mm	30.15 mm
self refresh	YES	YES	YES	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V
Minimum supply voltage (Vsup)	1.2825 V	1.2825 V	1.2825 V	1.2825 V	1.2825 V	1.2825 V	1.2825 V	1.2825 V	1.2825 V
Nominal supply voltage (Vsup)	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V
surface mount	NO	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maker	SAMSUNG	-	-	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG

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