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MC100ES6014EJR2

Description
Clock Drivers & Distribution FSL 1-5 Differential LVPECL Fanout Buffe
Categorylogic    logic   
File Size291KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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MC100ES6014EJR2 Overview

Clock Drivers & Distribution FSL 1-5 Differential LVPECL Fanout Buffe

MC100ES6014EJR2 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP20,.25
Contacts20
Manufacturer packaging codePGG20
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V
series100E
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length6.5 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals20
Actual output times5
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP20,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply+-2.5/+-3.3 V
Prop。Delay @ Nom-Sup0.525 ns
propagation delay (tpd)0.475 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.045 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.8 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
minfmax2000 MHz
Base Number Matches1
2.5 V/3.3 V 1:5 Differential
ECL/PECL/HSTL/LVDS Clock Driver
Product Discontinuance Notice – Last Time Buy Expires on (12/3/2013)
The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock
distribution in mind, accepting two clock sources into an input multiplexer. The
ECL/PECL input signals can be either differential or single-ended (if the V
BB
output is used). HSTL and LVDS inputs can be used when the ES6014 is
operating under PECL conditions.
The ES6014 specifically guarantees low output-to-output skew. Optimal
design, layout, and processing minimize skew within a device and from device to
device.
To ensure that the tight skew specification is realized, both sides of any
differential output need to be terminated identically into 50
even if only one
output is being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/disabled in the
LOW state. This avoids a runt clock pulse when the device is enabled/disabled
as can happen with an asynchronous control. The internal flip flop is clocked on
the falling edge of the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
The MC100ES6014, as with most other ECL devices, can be operated from a
positive V
CC
supply in PECL mode. This allows the ES6014 to be used for high
performance clock distribution in +3.3 V or +2.5 V systems. Single ended CLK
input pin operation is limited to a V
CC
3.0 V in PECL mode, or V
EE
–3.0 V in
ECL mode. Designers can take advantage of the ES6014's performance to
distribute low skew clocks across the backplane or the board.
Features
25 ps Within Device Skew
400 ps Typical Propagation Delay
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode: V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
ECL Mode: V
CC
= 0 V with V
EE
= –2.375 V to –3.8 V
LVDS and HSTL Input Compatible
Open Input Default State
20-Lead Pb-Free Package Available
Replacement part: ICS853S014I
MC100ES6014
DATA SHEET
MC100ES6014
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
ORDERING INFORMATION
Device
MC100ES6014EJ
MC100ES6014EJR2
Package
TSSOP-20 (Pb-Free)
TSSOP-20 (Pb-Free)
MC100ES6014 REVISION 4 DECEMBER 18, 2012
1
©2012 Integrated Device Technology, Inc.

MC100ES6014EJR2 Related Products

MC100ES6014EJR2 MC100ES6014EJ
Description Clock Drivers & Distribution FSL 1-5 Differential LVPECL Fanout Buffe Clock Drivers & Distribution FSL 1-5 Differential LVPECL Fanout Buffe
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction TSSOP, TSSOP20,.25 TSSOP, TSSOP20,.25
Contacts 20 20
Manufacturer packaging code PGG20 PGG20
Reach Compliance Code unknown unknown
ECCN code EAR99 EAR99
Other features ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V
series 100E 100E
Input adjustment DIFFERENTIAL MUX DIFFERENTIAL MUX
JESD-30 code R-PDSO-G20 R-PDSO-G20
JESD-609 code e3 e3
length 6.5 mm 6.5 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Humidity sensitivity level 1 1
Number of functions 1 1
Number of terminals 20 20
Actual output times 5 5
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP20,.25 TSSOP20,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260
power supply +-2.5/+-3.3 V +-2.5/+-3.3 V
Prop。Delay @ Nom-Sup 0.525 ns 0.525 ns
propagation delay (tpd) 0.475 ns 0.475 ns
Certification status Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.045 ns 0.045 ns
Maximum seat height 1.2 mm 1.2 mm
Maximum supply voltage (Vsup) 3.8 V 3.8 V
Minimum supply voltage (Vsup) 2.375 V 2.375 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V
surface mount YES YES
technology ECL ECL
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 4.4 mm 4.4 mm
minfmax 2000 MHz 2000 MHz
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