For air-conditioner fan motor
3-Phase Brushless Fan Motor
Driver
BM6203FS
General Description
This motor driver IC adopts PrestoMOS™ as the output
transistor, and put in a small full molding package with
the high voltage gate driver chip. The protection circuits
for overcurrent, overheating, under voltage lock out and
the high voltage bootstrap diode with current regulation
are built-in. It provides optimum motor drive system for a
wide variety of applications by the combination with
controller BD6201X series and enables motor unit
standardization.
Features
600V
PrestoMOS™ built-in
Output
current 2.5A
Bootstrap
operation by floating high side driver
(including diode)
3.3V
logic input compatible
Protection
circuits provided: OCP, TSD and UVLO
Fault
output (open drain)
Applications
Air
conditioners; air cleaners; water pumps;
dishwashers; washing machines
General
OA equipment
SSOP-A54_23
Key Specifications
Output
MOSFET Voltage:
600V
Driver
Output Current (DC):
±2.5A (Max)
Driver
Output Current (Pulse):
±4.0A (Max)
Output
MOSFET DC On Resistance:
1.7Ω (Typ)
Operating
Case Temperature:
-20°C to +100°C
Junction
Temperature:
+150°C
Power
Dissipation:
3.00W
Package
SSOP-A54_23
W (Typ) x D (Typ) x H (Max)
22.0 mm x 14.1 mm x 2.4 mm
Typical Application Circuit
VREG
FG
Q1
R1
R8
R9
C13
VSP
C1
DTR
BD6201XFS
C14
C7
C2~C4
C8
M
HW
HV
HU
R2
VREG
C11
C5
C9
C10
R5
R4
R3
VCC
GND
C6
D1
R7
C12
BM6203FS
R6
VDC
Figure 1. Application Circuit Example - BM6203FS & BD6201XFS
Product
structure : Semiconductor IC
This
product is not designed protection against radioactive rays
.
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TSZ02201-0828AB400110-1-2
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BM6203FS
Block Diagram and Pin Configuration
VDC
VCC
1
23
VDC
Datasheet
VCC
VCC
BU
22
VDC
FOB
2
FAULT
UH
UL
3
FOB
UH
BU
U
U
4
SDB
LEVEL SHIFT
&
GATE DRIVER
TRIP
21
UL
FAULT
BV
BV
20
VH
VL
6
V
7
SDB
VH
V
VL
LEVEL SHIFT
&
GATE DRIVER
TRIP
19
M
FAULT
18
VDC
BW
VDC
WH
17
WH 10
W
WL
11
SDB
LEVEL SHIFT
&
GATE DRIVER
TRIP
16
WL
FOB
BW
W
FOB 12
FAULT
PGND
15
VCC
GND
PGND
VCC 13
GND
14
Figure 2. Block Diagram
Figure 3. Pin Configuration
(Top View)
Pin Descriptions
(NC: No Connection)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name
VCC
FOB
UH
UL
NC
VH
VL
NC
NC
WH
WL
FOB
VCC
GND
Function
Low voltage power supply
Fault signal output (open drain)
Phase U high side control input
Phase U low side control input
Pin
23
-
22
-
21
Name
VDC
VDC
BU
U
U
BV
V
V
VDC
VDC
BW
W
W
PGND
Function
High voltage power supply
Phase U floating power supply
Phase U output
Phase V floating power supply
Phase V high side control input
Phase V low side control input
20
-
19
-
Phase V output
Phase W high side control input
Phase W low side control input
Fault signal output (open drain)
Low voltage power supply
Ground
18
17
-
16
15
High voltage power supply
Phase W floating power supply
Phase W output
Ground (current sense pin)
Note) All pin cut surfaces visible from the side of package are no connected, except the pin number is expressed as a “-”.
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BM6203FS
Functional Descriptions
1. Control Input Pins (UH, UL, VH, VL, WH, WL)
Datasheet
Truth Table
The input threshold voltages of the control pins are 2.5V and 0.8V, with a hysteresis
voltage of approximately 0.4V. The IC will accept input voltages up to the VCC voltage.
When the same phase control pins are input high at the same time, the high side and
low side gate driver outputs become low. Dead time is installed in the control signals.
The control input pins are connected internally to pull-down resistors (100kΩ nominal).
However, the switching noise on the output stage may affect the input on these pins and
cause undesired operation. In such cases, attaching an external pull-down resistor
(10kΩ recommended) between each control pin and ground, or connecting each pin to
an input voltage of 0.8V or less (preferably GND), is recommended.
2. Under Voltage Lock Out (UVLO) Circuit
HIN
L
H
L
H
LIN
L
L
H
H
HO
L
H
L
LO
L
L
H
Inhibition
Note) HIN: UH,VH,WH, LIN: UL,VL,WL
To secure the lowest power supply voltage necessary to operate the driver, and to prevent under voltage malfunctions,
the UVLO circuits are independently built into the upper side floating driver and the lower side driver. When the supply
voltage falls to V
UVL
or below, the controller forces driver outputs low. When the voltage rises to V
UVH
or above, the UVLO
circuit ends the lockout operation and returns the chip to normal operation. Even if the controller returns to normal
operation, the output begins from the following control input signal.
VCC
V
CCUVH
V
CCUVL
HIN
LIN
HO
LO
VB
V
BUVH
V
BUVL
HIN
LIN
HO
LO
Figure 4. Low Voltage Monitor - UVLO - Timing Chart
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TSZ02201-0828AB400110-1-2
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BM6203FS
3. Bootstrap Operation
VB
DX
HO
L
VS
VCC
LO
H
ON
L
VCC
LO
OFF
OFF
H
VS
C
B
VDC
DX
HO
ON
VB
C
B
VDC
Datasheet
Figure 5. Charging Period
Figure 6. Discharging Period
The bootstrap is operated by the charge period and the discharge period being alternately repeated for bootstrap
capacitor (CB) as shown in the figure above. In a word, this operation is repeated while the output of an external
transistor is switching with synchronous rectification. Because the supply voltage of the floating driver is charged from the
VCC power supply to CB through prevention of backflow diode DX, it is approximately (VCC-1V).
The resistance series connection with DX has the impedance of approximately 200
Ω.
The capacitance value for the bootstrap is the following formula:
( I
BBQ
I
LBD
)
C
BOOT
»
F
PWM
2
Q
g
Q
LOSS
36 nF
V
DROP
where, for example:
I
BBQ
is the floating driver power supply quiescence current, 150µA(Max)
I
LBD
is the bootstrap diode reverse bias current, 10µA(Max)
F
PWM
is the carrier frequency, 20kHz
Q
g
is the output MOSFET total gate charge, 50nC(Max)
Q
LOSS
is the floating driver transmission loss, 1nC(Max)
∆V
DROP
is the drop voltage of the floating driver power supply, 3V
The allowed drop voltage actually becomes smaller by the range of the used power supply voltage, the output MOSFET
ON resistance, the forward voltages of the internal boot diode (the drop voltage to the capacitor by the charge current),
and the power supply voltage monitor circuits etc. Please set the calculation value to the criterion about the capacitance
value tenfold or more to secure the margin in consideration of temperature characteristics and the value change, etc.
Moreover, the example of the mentioned above assumes the synchronous rectification switching. Because the total gate
charge is needed only by the carrier frequency in the upper switching section, for example 150° commutation driving, it
becomes a great capacity shortage in the above settings. Please set it after confirming actual application operation.
4. Thermal Shutdown (TSD) Circuit
The TSD circuit operates when the junction temperature of the gate driver exceeds the preset temperature (150°C
nominal). At this time, the controller forces all driver outputs low. Since thermal hysteresis is provided in the TSD circuit,
the chip returns to normal operation when the junction temperature falls below the preset temperature (125°C nominal).
The TSD circuit is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or
guarantee its operation in the presence of extreme heat. Do not continue using the IC after the TSD circuit is activated,
and do not use the IC in an environment where activation of the circuit is assumed. Moreover, it is not possible to follow
the output MOSFET junction temperature rising rapidly because it is a gate driver chip that monitors the temperature and
it is likely not to function effectively.
5. Overcurrent Protection (OCP) Circuit
The overcurrent protection circuit can be activated by connecting a low value resistor for current detection between the
PGND pin and the GND pin. When the PGND pin voltage reaches or surpasses the threshold value (0.9V typical), the
gate driver outputs low to the gate of all output MOSFETs, thus initiating the overcurrent protection operation.
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BM6203FS
6. Fault Signal Output
Datasheet
When the gate driver detects either state that should be protected (UVLO / TSD / OCP), the FOB pin outputs low (open
drain) for at least 25µs nominal. The FOB pin has wired-OR connection with each phase gate driver chip internally, and
into another phase also entering the protection operation. Even when this function is not used, the FOB pin is pull-up to
the voltage of 3V or more and at least a resistor with a value 10k
Ω
or more. Moreover, the signal from the outside of the
chip is not passed because of the built-in analog filter, but the internal control signals (UVLO / TSD / OCP) pass the filter
(2.0µs Min.) for the malfunction prevention by the switching noise, etc.
TSD
OCP
UVLO
FILTER
SHUTDOWN
FOB
FAULT
Figure 7. Fault Signal Bi-Directional Input Pin Interface
HIN
LIN
HO
LO
2.0µs (Min)
0.9V(Typ)
2.0µs (Min)
PGND
FOB
25µs (Typ)
25µs (Typ)
Figure 8. Fault Operation ~ OCP ~ Timing Chart
10
9
8
Release time : t [ms]
The release time from the protection operation can be
changed by inserting an external capacitor. Refer to
the formula below. Release time of 5ms or more is
recommended.
t
½
ln( 1
2 .0
)
R
C
[s]
VPU
VPU=5V
VPU=15V
7
6
5
4
3
2
VPU
R
FOB
C
1
0
0.01
0.10
Capacitance : C[µF]
1.00
Figure 9. Release Time Setting Application Circuit
Figure 10. Release Time (Reference Data @R=100kΩ)
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