consists of a line transmitter and receiver integrated
on a single chip and is designed for DS3, E3 or
SONET STS-1 applications.
XRT73LC00A can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
In the transmit direction, the XRT73LC00A encodes
input data to either B3ZS (for DS3/STS-1
applications) or HDB3 (for E3 applications) format
and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction the XRT73LC00A performs
equalization on incoming signals, performs Clock
Recovery, decodes data from either B3ZS or HDB3
format, converts the receive data into TTL/CMOS
format, checks for LOS or LOL conditions and detects
and declares the occurrence of line code violations.
The XRT73LC00A also contains a 4-Wire
Microprocessor Serial Interface for accessing the on-
chip Command registers.
FEATURES
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L00A
Meets
E3/DS3/STS-1
Requirements
Jitter
Tolerance
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Contains a 4-Wire Microprocessor Serial Interface
Uses Minimum External components
Low Power CMOS Design
Single +3.3V Power Supply
5 V Tolerant pins
-40°C to +85°C Operating Temperature Range
Available in a 44 pin TQFP package
APPLICATIONS
Interfaces to E3, DS3 or SONET STS-1 Networks
CSU/DSU Equipment
PCM Test Equipment
Fiber Optic Terminals
Multiplexers
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT73LC00A
E3
STS-1/DS3
Host/(HW )
RLOL EXCLK
ICT
RCLKINV
REV. 1.0.2
RTIP
RRING
AGC/
Equalizer
Slicer
Clock
Recovery
RCLK1
Invert
LCV/(RCLK2)
Data
Recovery
REQDIS
Peak
Detector
LOS Detector
HDB3/
B3ZS
Decoder
RPOS
RNEG
DR/SR
LOSTHR
SDI
SDO/(LCV)
SClk
CS
REGRESET
Serial
Processor
Interface
RLOS
Loop MUX
LLB
RLB
ENDECDIS
TAOS
TTIP
Pulse
Shaping
TRING
HDB3/
B3ZS
Encoder
Transm it
Logic
Duty Cycle Adjust
TPDATA
TNDATA
TClk
M TIP
M RING
DM O
Device
Monitor
Tx
Control
TXLEV
TXOFF
ORDERING INFORMATION
P
ART
N
UMBER
XRT73LC00AIV
P
ACKAGE
T
YPE
44 Pin TQFP (10mm x 10mm)
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
2
XRT73LC00A
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT
F
IGURE
2. P
IN
O
UT OF THE
XRT73LC00A
IN THE
44 P
IN
TQFP
TxAGND
TNDATA
TxAVDD
TPDATA
MRING
TXOFF
TRING
TCLK
MTIP
TTIP
44
43
42
41
40
39
38
37
36
35
34
TxLEV
TAOS
TxAVDD
DMO
TxAGND
AGND
RxAGND
RTIP
RRING
RxAVDD
REGRESET/
RCLK2INV
1
2
3
4
5
6
7
8
9
10
11
ICT
33
32
31
30
29
28
27
26
25
24
23
RPOS
RNEG
RCLK1
LCV/(RCLK2)
RxDVDD
RxDGND
EXCLK
DVDD
DGND
RLOS
RLOL
XRT73LC00A
(Top View)
12
REQDIS
13
LOSTHR
14
LLB
15
RLB
16
STS1/DS3
17
E3
18
HOST/HW
19
SDI/(LOSMUTEN)
20
SDO/(LCV)
21
SCLK/(ENDECDIS)
22
CS/(DR/SR)
3
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE OF CONTENTS
FEATURES ..................................................................................................................................................1
3.7 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIP-
MENT .............................................................................................................................................................. 41
4.4 TXOFF FEATURES ........................................................................................................................................ 47
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Microcontroller MCU
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