xr
DECEMBER 2005
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
REV. 1.0.3
GENERAL DESCRIPTION
The XRT75L02 is a two-channel fully integrated Line
Interface Unit (LIU) with Jitter Attenuator for E3/DS3/
STS-1 applications. It incorporates independent
Receivers, Transmitters and Jitter Attenuators in a
single 100 pin TQFP package.
The XRT75L02 can be configured to operate in either
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz) modes.The transmitter can be turned off (tri-
stated) for redundancy support and for conserving
power.
The XRT75L02’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L02 incorporates advanced crystal-less
jitter attenuators that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications.
The XRT75L02 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L02 supports local,remote and digital
loop-backs. The XRT75L02 also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
•
Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
•
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
•
Provides low jitter output clock.
TRANSMITTER:
•
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
•
Tri-state Transmit output capability for redundancy
applications
•
Transmitters can be turned on or off.
JITTER ATTENUATOR:
•
On chip advanced crystal-less Jitter Attenuator.
•
Jitter Attenuator can be selected in Receive or
Transmit paths.
•
16 or 32 bits selectable FIFO size.
•
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
•
Jitter Attenuators can be disabled.
CONTROL AND DIAGNOSTICS:
•
5 wire Serial Microprocessor Interface for control
and configuration.
•
Supports
Monitoring.
optional
internal
Transmit
Driver
FEATURES
RECEIVER:
•
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
•
Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
•
PRBS error counter register to accumulate errors.
•
Hardware Mode for control and configuration.
•
Supports Local, Remote and Digital Loop-backs.
•
Single 3.3 V ± 5% power supply.
•
5 V Tolerant I/O.
•
Available in 100 pin TQFP.
•
-40°C to 85°C Industrial Temperature Range.
APPLICATIONS
•
E3/DS3 Access Equipment.
•
STS1-SPE to DS3 Mapper.
•
DSLAMs.
•
Digital Cross Connect Systems.
•
CSU/DSU Equipment.
•
Routers.
•
Fiber Optic Terminals.
•
Detects and Clears LOS as per G.775.
•
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
•
On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
•
On-chip
clock
synthesizer
generates
the
appropriate rate clock from a single frequency
XTAL.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
xr
REV. 1.0.3
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT 75L02
SDI
SDO
INT
SClk
CS
RESET
HOST/HW
STS-1/DS3
E3
REQEN
RTIP
RRING
SR/DR
LLB
XRT75L03
Serial
Processor
Interface
CLK_OUT
E3Clk,DS3Clk,
STS-1Clk
RLOL
RxON
RxClkINV
Peak Detector
Slicer
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
Attenuator
Invert
HDB3/
B3ZS
Decoder
RxClk
RPOS
RNEG/
LCV
AGC/
Equalizer
MUX
Local
LoopBack
Remote
LoopBack
RLB
RLOS
JATx/Rx
TPOS
TNEG
TxClk
TAOS
TxLEV
TxON
TTIP
TRING
MTIP
MRING
DMO
Line
Driver
Tx
Pulse
Shaping
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
Device
Monitor
Tx
Control
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
TRANSMIT INTERFACE CHARACTERISTICS
•
Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
•
Integrated Pulse Shaping Circuit.
•
Built-in B3ZS/HDB3 Encoder (which can be disabled).
•
Accepts Transmit Clock with duty cycle of 30%-70%.
•
Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications.
•
Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499
-CORE
and
ANSI T1.102_1993.
•
Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE.
•
Transmitter can be turned off in order to support redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
•
Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery.
•
Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications.
•
Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications.
•
Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications.
•
Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms.
•
Built-in B3ZS/HDB3 Decoder (which can be disabled).
2
xr
REV. 1.0.3
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
•
Recovered Data can be muted while the LOS Condition is declared.
•
Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment.
F
IGURE
2. P
IN
O
UT OF THE
XRT75L02
TNEG_0
TPOS_0
TxCLK_0
DMO_0
CLKOUT_0
TxON
TxMON
TxAGND_0
TxAVDD_0
JAAGND_0
JAAVDD_0
JADVDD_0
JADGND_0
RxDVDD_0
RxDGND_0
RxCLK_0
RPOS_0
RNEG/LCV_0
RLOS_0
RLOL_0
TEST
RESET
ICT
SFM_EN
SR/DR
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TAOS_0
TxLEV_0
MRING_0
MTIP_0
TRING_0
TTIP_0
TxDVDD_0
TxDGND_0
DVDD
E3CLK
DGND
DGND
DS3CLK
DVDD
DVDD
STS1CLK/SFMCLK
DGND
TxDGND_1
TxDVDD_1
TTIP_1
TRING_1
MTIP_1
MRING_1
TxLEV_1
TAOS_1
XRT75L02
TNEG_1
TPOS_1
TxCLK_1
DMO_1
CLKOUT_1
CLKOUT_EN
TxAGND_1
TxAVDD_1
JAAGND_1
JAAVDD_1
JADVDD_1
JADGND_1
DVDD_1
DGND_1
RxCLK_1
RPOS_1
RNEG/LCV_1
RLOS_1
RLOL_1
SDI/RxON
SCLK/TxCLKINV
CS/RxCLKINV
INT/LOSMUT
SDO/RxMON
HOST/HW
P
ART
N
UMBER
XRT75L02IV
REQEN_0
E3_0
STS1/DS3_0
LLB_0
RLB_0
RxAVDD_0
RxAGND_0
RRING_0
RTIP_0
AGND
RxA
RxB
AVDD
JA_0
JA_1
JATx/Rx
RTIP_1
RRING_1
RxAGND_1
RxAVDD_1
RLB_1
LLB_1
STS1/DS3_1
E3_1
REQEN_1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ORDERING INFORMATION
P
ACKAGE
14mm x 14mm 100 Pin TQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
3
xr
REV. 1.0.3
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
F
EATURES
..................................................................................................................................................... 1
A
PPLICATIONS
............................................................................................................................................... 1
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
....................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
......................................................................................................... 2
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT 75L02 .............................................................................................................................. 2
F
IGURE
2. P
IN
O
UT OF THE
XRT75L02............................................................................................................................................ 3
ORDERING INFORMATION .................................................................................................................... 3
T
ABLE OF
C
ONTENTS
............................................................................................................
I
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
T
RANSMIT
I
NTERFACE
.................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
...................................................................................................................................... 6
C
LOCK
I
NTERFACE
......................................................................................................................................... 8
CONTROL AND ALARM INTERFACE........................................................................................................ 9
M
ODE
S
ELECT
............................................................................................................................................ 11
M
ICROPROCESSOR
S
ERIAL
INTERFACE - (HOST MODE)......................................................................... 11
J
ITTER
A
TTENUATOR INTERFACE
.................................................................................................................. 12
A
NALOG
P
OWER AND
G
ROUND
.................................................................................................................... 13
DIGITAL
P
OWER AND
G
ROUND
...................................................................................................................... 13
1.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 15
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
......................................................................................................................................... 15
T
ABLE
2: DC E
LECTRICAL
C
HARACTERISTICS
: ................................................................................................................................ 15
2.0 TIMING CHARACTERISTICS .............................................................................................................. 16
F
IGURE
3.
F
IGURE
4.
F
IGURE
5.
F
IGURE
6.
T
YPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE
XRT75L02 (
DUAL
-
RAIL DATA
) .......................................... 16
T
RANSMITTER
T
ERMINAL
I
NPUT
T
IMING
.......................................................................................................................... 16
R
ECEIVER
D
ATA OUTPUT AND CODE VIOLATION TIMING
................................................................................................... 17
T
RANSMIT
I
NTERFACE CIRCUIT FOR
E3, DS3
AND
STS-1 R
ATES
.................................................................................... 17
3.0 LINE SIDE CHARACTERISTICS: ....................................................................................................... 18
3.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 18
F
IGURE
7. P
ULSE
M
ASK FOR
E3 (34.368
MBITS
/
S
)
INTERFACE AS PER ITU
-
T
G.703......................................................................... 18
T
ABLE
3: E3 T
RANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
....................................................... 18
F
IGURE
8. B
ELLCORE
GR-253 CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE FOR
SONET STS-1 A
PPLICATIONS
............................ 19
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
..................................................................................................................................... 19
T
ABLE
5: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) .............................. 20
F
IGURE
9. T
RANSMIT
O
UPUT
P
ULSE
T
EMPLATE FOR
DS3
AS PER
B
ELLCORE
GR-499 ..................................................................... 20
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................ 21
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) ................................. 21
F
IGURE
10. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
S
TRUCTURE
..................................................................................................... 22
F
IGURE
11. T
IMING
D
IAGRAM FOR THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................ 22
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V± 5%
AND LOAD
= 10
P
F) .................................. 23
4.0 THE TRANSMITTER SECTION: ......................................................................................................... 24
4.1 TRANSMIT CLOCK: ....................................................................................................................................... 24
4.2 B3ZS/HDB3 ENCODER: ................................................................................................................................ 24
4.2.1 B3ZS ENCODING: ...................................................................................................................................................... 24
F
IGURE
12. S
INGLE
-R
AIL OR
NRZ D
ATA
F
ORMAT
(E
NCODER AND
D
ECODER ARE
E
NABLED
)............................................................ 24
F
IGURE
13. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER AND DECODER ARE DISABLED
) ............................................................................. 24
4.2.2 HDB3 ENCODING:...................................................................................................................................................... 25
4.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 25
F
IGURE
14. B3ZS E
NCODING
F
ORMAT
........................................................................................................................................... 25
F
IGURE
15. HDB3 E
NCODING
F
ORMAT
.......................................................................................................................................... 25
4.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT: ................................................................................. 26
4.3.2 INTERFACING TO THE LINE:.................................................................................................................................... 26
4.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 26
F
IGURE
16. T
RANSMIT
D
RIVER
M
ONITOR SET
-
UP
. ........................................................................................................................... 26
4.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 27
5.0 THE RECEIVER SECTION: ................................................................................................................. 27
5.1 AGC/EQUALIZER: .......................................................................................................................................... 27
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 27
I
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
xr
REV. 1.0.3
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 28
F
IGURE
17. I
NTERFERENCE
M
ARGIN
T
EST
S
ET UP FOR
DS3/STS-1................................................................................................ 28
F
IGURE
18. I
NTERFERENCE
M
ARGIN
T
EST
S
ET UP FOR
E3.............................................................................................................. 28
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
........................................................................................................................... 28
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................. 29
5.4 LOS (LOSS OF SIGNAL) DETECTOR: .......................................................................................................... 29
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 29
D
ISABLING
ALOS/DLOS D
ETECTION
:...........................................................................................................29
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 29
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION AND
C
LEARANCE
T
HRESHOLDS FOR A GIVEN SETTING OF
REQEN (DS3
AND
STS-1
A
PPLICATIONS
) ............................................................................................................................................................... 29
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION: ................................................................................... 30
F
IGURE
19. L
OSS
O
F
S
IGNAL
D
EFINITION FOR
E3
AS PER
ITU-T G.775.......................................................................................... 30
F
IGURE
20. L
OSS OF
S
IGNAL
D
EFINITION FOR
E3
AS PER
ITU-T G.775. ......................................................................................... 30
6.0 JITTER: ................................................................................................................................................31
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 31
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS: ............................................................................................... 31
F
IGURE
21. J
ITTER
T
OLERANCE
M
EASUREMENTS
............................................................................................................................ 31
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 32
F
IGURE
22. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1 ................................................................................................................ 32
F
IGURE
23. I
NPUT
J
ITTER
T
OLERANCE FOR
E3 .............................................................................................................................. 32
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 33
6.3 JITTER GENERATION: .................................................................................................................................. 33
6.4 JITTER ATTENUATOR: ................................................................................................................................. 33
T
ABLE
11: J
ITTER
A
MPLITUDE VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
)................................................................... 33
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
............................................................................................................. 33
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
.................................................................................................................................... 34
F
IGURE
24. J
ITTER
T
RANSFER
R
EQUIREMENTS AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
................................................................ 34
7.0 SERIAL HOST INTERFACE: ...............................................................................................................35
T
ABLE
14:
T
ABLE
15:
T
ABLE
16:
T
ABLE
17:
T
ABLE
18:
T
ABLE
19:
F
UNCTIONS OF SHARED PINS
......................................................................................................................................... 35
R
EGISTER
M
AP AND
B
IT
N
AMES
.................................................................................................................................... 35
R
EGISTER
M
AP
D
ESCRIPTION
- G
LOBAL
......................................................................................................................... 36
R
EGISTER
M
AP AND
B
IT
N
AMES
- C
HANNEL
0 R
EGISTERS
.............................................................................................. 36
R
EGISTER
M
AP AND
B
IT
N
AMES
- C
HANNEL
1 R
EGISTERS
.............................................................................................. 37
R
EGISTER
M
AP
D
ESCRIPTION
- C
HANNEL
0.................................................................................................................... 38
8.0 DIAGNOSTIC FEATURES: ..................................................................................................................42
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 42
8.2 LOOPBACKS: ................................................................................................................................................. 42
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 42
F
IGURE
25. PRBS MODE ............................................................................................................................................................. 42
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 43
8.2.3 IREMOTE LOOPBACK:.............................................................................................................................................. 43
F
IGURE
26. A
NALOG
L
OOPBACK
..................................................................................................................................................... 43
F
IGURE
27. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 43
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 44
F
IGURE
28. R
EMOTE
L
OOPBACK
.................................................................................................................................................... 44
F
IGURE
29. T
RANSMIT
A
LL
O
NES
(TAOS) ...................................................................................................................................... 44
T
ABLE
20: TRANSFORMER RECOMMENDATIONS .................................................................................................................. 45
T
ABLE
21: T
RANSFORMER
D
ETAILS
................................................................................................................................................ 45
ORDERING INFORMATION.............................................................................................47
PACKAGE DIMENSIONS.................................................................................................47
R
EVISION
H
ISTORY
.......................................................................................................................................48
II