XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
MAY 2011
REV. 1.0.2
GENERAL DESCRIPTION
The XRT73LC00A DS3/E3/STS-1 Line Interface Unit
is a low power CMOS version of the XRT73L00A and
consists of a line transmitter and receiver integrated
on a single chip and is designed for DS3, E3 or
SONET STS-1 applications.
XRT73LC00A can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
In the transmit direction, the XRT73LC00A encodes
input data to either B3ZS (for DS3/STS-1
applications) or HDB3 (for E3 applications) format
and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction the XRT73LC00A performs
equalization on incoming signals, performs Clock
Recovery, decodes data from either B3ZS or HDB3
format, converts the receive data into TTL/CMOS
format, checks for LOS or LOL conditions and detects
and declares the occurrence of line code violations.
The XRT73LC00A also contains a 4-Wire
Microprocessor Serial Interface for accessing the on-
chip Command registers.
FEATURES
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L00A
Meets
E3/DS3/STS-1
Requirements
Jitter
Tolerance
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Contains a 4-Wire Microprocessor Serial Interface
Uses Minimum External components
Low Power CMOS Design
Single +3.3V Power Supply
5 V Tolerant pins
-40°C to +85°C Operating Temperature Range
Available in a 44 pin TQFP package
APPLICATIONS
Interfaces to E3, DS3 or SONET STS-1 Networks
CSU/DSU Equipment
PCM Test Equipment
Fiber Optic Terminals
Multiplexers
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT73LC00A
E3
STS-1/DS3
Host/(HW )
RLOL EXCLK
ICT
RCLKINV
REV. 1.0.2
RTIP
RRING
AGC/
Equalizer
Slicer
Clock
Recovery
RCLK1
Invert
LCV/(RCLK2)
Data
Recovery
REQDIS
Peak
Detector
LOS Detector
HDB3/
B3ZS
Decoder
RPOS
RNEG
DR/SR
LOSTHR
SDI
SDO/(LCV)
SClk
CS
REGRESET
Serial
Processor
Interface
RLOS
Loop MUX
LLB
RLB
ENDECDIS
TAOS
TTIP
Pulse
Shaping
TRING
HDB3/
B3ZS
Encoder
Transm it
Logic
Duty Cycle Adjust
TPDATA
TNDATA
TClk
M TIP
M RING
DM O
Device
Monitor
Tx
Control
TXLEV
TXOFF
ORDERING INFORMATION
P
ART
N
UMBER
XRT73LC00AIV
P
ACKAGE
T
YPE
44 Pin TQFP (10mm x 10mm)
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
2
XRT73LC00A
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT
F
IGURE
2. P
IN
O
UT OF THE
XRT73LC00A
IN THE
44 P
IN
TQFP
TxAGND
TNDATA
TxAVDD
TPDATA
MRING
TXOFF
TRING
TCLK
MTIP
TTIP
44
43
42
41
40
39
38
37
36
35
34
TxLEV
TAOS
TxAVDD
DMO
TxAGND
AGND
RxAGND
RTIP
RRING
RxAVDD
REGRESET/
RCLK2INV
1
2
3
4
5
6
7
8
9
10
11
ICT
33
32
31
30
29
28
27
26
25
24
23
RPOS
RNEG
RCLK1
LCV/(RCLK2)
RxDVDD
RxDGND
EXCLK
DVDD
DGND
RLOS
RLOL
XRT73LC00A
(Top View)
12
REQDIS
13
LOSTHR
14
LLB
15
RLB
16
STS1/DS3
17
E3
18
HOST/HW
19
SDI/(LOSMUTEN)
20
SDO/(LCV)
21
SCLK/(ENDECDIS)
22
CS/(DR/SR)
3
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE OF CONTENTS
FEATURES ..................................................................................................................................................1
APPLICATIONS ...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT73LC00A .......................................................................................................................... 2
ORDERING INFORMATION...............................................................................................2
F
IGURE
2. P
IN
O
UT OF THE
XRT73LC00A
IN THE
44 P
IN
TQFP ...................................................................................................... 3
PIN DESCRIPTION.............................................................................................................4
ELECTRICAL CHARACTERISTICS ................................................................................12
ABSOLUTE MAXIMUM RATINGS .........................................................................................................12
DC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................12
AC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................13
F
IGURE
3. T
IMING
D
IAGRAM OF THE
T
RANSMIT
T
ERMINAL
I
NPUT
I
NTERFACE
.................................................................................... 14
F
IGURE
4. T
IMING
D
IAGRAM OF THE
R
ECEIVE
T
ERMINAL
O
UTPUT
I
NTERFACE
.................................................................................. 14
F
IGURE
5. T
RANSMIT
P
ULSE
A
MPLITUDE
T
EST
C
IRCUIT FOR
DS3, E3
AND
STS-1 R
ATES
................................................................ 14
AC ELECTRICAL CHARACTERISTICS (CONT’D) L
INE
S
IDE
P
ARAMETERS
.............................................17
F
IGURE
6. ITU-T G.703 T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE FOR
E3 A
PPLICATIONS
..................................................................... 18
F
IGURE
7. B
ELLCORE
GR-499-CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE FOR
DS3 A
PPLICATIONS
............................................. 18
F
IGURE
8. B
ELLCORE
GR-253-CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE FOR
SONET STS-1 A
PPLICATIONS
............................ 19
F
IGURE
9. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
D
ATA
S
TRUCTURE
.............................................................................................. 19
AC ELECTRICAL CHARACTERISTICS (CONT.) .....................................................................................20
F
IGURE
10. T
IMING
D
IAGRAM FOR THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................ 20
SYSTEM DESCRIPTION ..................................................................................................21
T
HE
T
RANSMIT
S
ECTION
...............................................................................................................................21
T
HE
R
ECEIVE
S
ECTION
.................................................................................................................................21
T
HE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
..................................................................................................21
T
ABLE
1: R
OLE OF
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE PINS WHEN THE
XRT73LC00A
IS OPERATING IN THE
H
ARDWARE
M
ODE
.. 22
1.0 SELECTING THE DATA RATE ............................................................................................................23
T
ABLE
2: S
ELECTING THE
D
ATA
R
ATE FOR THE
XRT73LC00A
VIA THE
E3
AND
STS-1/DS3
INPUT PINS
(H
ARDWARE
M
ODE
) ........... 23
C
OMMAND
R
EGISTER
CR4 (A
DDRESS
= 0
X
04) .............................................................................................23
T
ABLE
3: S
ELECTING THE
D
ATA
R
ATE FOR THE
XRT73LC00A V
IA THE
STS-1/DS3
AND THE
E3 B
IT
-
FIELDS
W
ITHIN
C
OMMAND
R
EGISTER
CR4 (HOST M
ODE
) ....................................................................................................................................................... 24
2.0 THE TRANSMIT SECTION ..................................................................................................................24
2.1 THE TRANSMIT LOGIC BLOCK .................................................................................................................... 24
F
IGURE
11. T
HE
T
YPICAL
I
NTERFACE FOR THE
T
RANSMISSION OF
D
ATA IN A
D
UAL
-R
AIL
F
ORMAT
F
ROM THE
T
RANSMITTING
T
ERMINAL
E
QUIPMENT TO THE
T
RANSMIT
S
ECTION OF THE
XRT73LC00A ....................................................................................... 25
F
IGURE
12. H
OW THE
XRT73LC00A S
AMPLES THE
D
ATA ON THE
TPDATA
AND
TNDATA I
NPUT
P
INS
.......................................... 25
2.1.1 ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT ............................................................... 25
C
OMMAND
R
EGISTER
CR1 (A
DDRESS
= 0
X
01) .............................................................................................26
F
IGURE
13. T
HE
B
EHAVIOR OF THE
TPDATA
AND
TCLK I
NPUT
S
IGNALS
W
HILE THE
T
RANSMIT
L
OGIC
B
LOCK IS
A
CCEPTING
S
INGLE
-R
AIL
D
ATA
F
ROM THE
T
ERMINAL
E
QUIPMENT
.......................................................................................................................... 26
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY .................................................................... 26
2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................................ 26
2.3.1 B3ZS ENCODING ....................................................................................................................................................... 26
F
IGURE
14. A
N
E
XAMPLE OF
B3ZS E
NCODING
............................................................................................................................... 27
2.3.2 HDB3 ENCODING....................................................................................................................................................... 27
F
IGURE
15. A
N
E
XAMPLE OF
HDB3 E
NCODING
.............................................................................................................................. 27
2.3.3 ENABLING/DISABLING THE HDB3/B3ZS ENCODER ............................................................................................. 27
C
OMMAND
R
EGISTER
CR2 (A
DDRESS
= 0
X
02) .............................................................................................28
2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY ............................................................................................ 28
2.4.1
C
OMMAND
2.4.2
C
OMMAND
2.4.3
2.4.4
ENABLING THE TRANSMIT LINE BUILD-OUT CIRCUIT ......................................................................................... 28
R
EGISTER
CR1 (A
DDRESS
= 0
X
01) .............................................................................................28
DISABLING THE TRANSMIT LINE BUILD-OUT CIRCUIT ........................................................................................ 29
R
EGISTER
CR1 (A
DDRESS
= 0
X
01) .............................................................................................29
DESIGN GUIDELINE FOR SETTING THE TRANSMIT LINE BUILD-OUT CIRCUIT ................................................ 29
THE TRANSMIT LINE BUILD-OUT CIRCUIT AND E3 APPLICATIONS................................................................... 29
2.5 INTERFACING THE TRANSMIT SECTION OF THE XRT73LC00A TO THE LINE ...................................... 29
F
IGURE
16. R
ECOMMENDED
S
CHEMATIC FOR
I
NTERFACING THE
T
RANSMIT
S
ECTION OF THE
XRT73LC00A
TO THE
L
INE
................. 30
T
RANSFORMER
R
ECOMMENDATIONS
................................................................................................... 30
3.0 THE RECEIVE SECTION .....................................................................................................................32
I
XRT73LC00A
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT
3.1 INTERFACING THE RECEIVE SECTION OF THE XRT73LC00A TO THE LINE ......................................... 32
F
IGURE
17. R
ECOMMENDED
S
CHEMATIC FOR
I
NTERFACING THE
R
ECEIVE
S
ECTION OF THE
XRT73LC00A
TO THE
L
INE
(T
RANSFORMER
-
C
OUPLING
)..................................................................................................................................................................... 32
F
IGURE
18. R
ECOMMENDED
S
CHEMATIC FOR
I
NTERFACING THE
R
ECEIVE
S
ECTION OF THE
XRT73LC00A
TO THE
L
INE
(C
APACITIVE
-C
OU
-
PLING
)............................................................................................................................................................................ 33
3.2 THE RECEIVE EQUALIZER BLOCK ............................................................................................................. 33
3.2.1 GUIDELINES FOR SETTING THE RECEIVE EQUALIZER ....................................................................................... 33
F
IGURE
19. T
HE
T
YPICAL
A
PPLICATION FOR THE
S
YSTEM
I
NSTALLER
............................................................................................. 34
C
OMMAND
R
EGISTER
CR2 (A
DDRESS
= 0
X
02)............................................................................................. 35
3.3 PEAK DETECTOR AND SLICER ................................................................................................................... 35
3.4 CLOCK RECOVERY PLL ............................................................................................................................... 35
3.5 THE HDB3/B3ZS DECODER ......................................................................................................................... 36
3.5.1 B3ZS DECODING DS3/STS-1 APPLICATIONS ........................................................................................................ 36
F
IGURE
20. A
N
E
XAMPLE OF
B3ZS D
ECODING
............................................................................................................................... 36
3.5.2 HDB3 DECODING E3 APPLICATIONS...................................................................................................................... 36
F
IGURE
21. A
N
E
XAMPLE OF
HDB3 D
ECODING
.............................................................................................................................. 37
3.5.3 ENABLING/DISABLING THE HDB3/B3ZS DECODER ............................................................................................. 37
C
OMMAND
R
EGISTER
CR2 (A
DDRESS
= 0
X
02)............................................................................................. 37
3.6 LOS DECLARATION/CLEARANCE .............................................................................................................. 37
3.6.1 THE LOS DECLARATION/CLEARANCE CRITERIA FOR E3 APPLICATIONS....................................................... 38
F
IGURE
22. T
HE
S
IGNAL
L
EVELS THAT THE
XRT73LC00A D
ECLARES AND
C
LEARS
LOS (E3 M
ODE
O
NLY
)..................................... 38
F
IGURE
23. T
HE
B
EHAVIOR OF THE
LOS O
UTPUT
I
NDICATOR
I
N
R
ESPONSE TO THE
L
OSS OF
S
IGNAL AND THE
R
ESTORATION OF
S
IGNAL
39
3.6.2 THE LOS DECLARATION/CLEARANCE CRITERIA FOR DS3 AND STS-1 APPLICATIONS ................................ 39
T
ABLE
4: T
HE
ALOS (A
NALOG
LOS) D
ECLARE AND
C
LEAR
T
HRESHOLDS FOR A GIVEN SETTING OF
LOSTHR
AND
REQEN
FOR
DS3
AND
STS-1 A
PPLICATIONS
..................................................................................................................................................... 39
C
OMMAND
R
EGISTER
CR0 (A
DDRESS
= 0
X
00)............................................................................................. 40
C
OMMAND
R
EGISTER
CR2 (A
DDRESS
= 0
X
02)............................................................................................. 40
C
OMMAND
R
EGISTER
CR0 (A
DDRESS
= 0
X
00)............................................................................................. 40
C
OMMAND
R
EGISTER
CR2 (A
DDRESS
= 0
X
02)............................................................................................. 41
3.6.3 MUTING THE RECOVERED DATA WHILE THE LOS IS BEING DECLARED......................................................... 41
C
OMMAND
R
EGISTER
CR3 (A
DDRESS
= 0
X
03)............................................................................................. 41
3.7 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIP-
MENT .............................................................................................................................................................. 41
F
IGURE
24. T
HE
T
YPICAL
I
NTERFACE FOR THE
T
RANSMISSION OF
D
ATA IN A
D
UAL
-R
AIL
F
ORMAT
F
ROM THE
R
ECEIVE
S
ECTION OF THE
XRT73LC00A
TO THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
................................................................................................ 42
F
IGURE
25. H
OW THE
XRT73LC00A O
UTPUTS
D
ATA ON THE
RPOS
AND
RNEG O
UTPUT
P
INS
.................................................... 42
F
IGURE
26. T
HE
B
EHAVIOR OF THE
RPOS, RNEG
AND
RCLK1 S
IGNALS
W
HEN
RCLK1
IS
I
NVERTED
............................................ 43
C
OMMAND
R
EGISTER
CR3 (A
DDRESS
= 0
X
03)............................................................................................. 43
3.7.1 ROUTING SINGLE-RAIL FORMAT DATA (BINARY DATA STREAM) TO THE RECEIVE TERMINAL EQUIPMENT 43
C
OMMAND
R
EGISTER
CR3 (A
DDRESS
= 0
X
03)............................................................................................. 43
F
IGURE
27. T
HE
T
YPICAL
I
NTERFACE FOR THE
T
RANSMISSION OF
D
ATA IN A
S
INGLE
-R
AIL
F
ORMAT
F
ROM THE
R
ECEIVE
S
ECTION OF THE
XRT73LC00A
TO THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
................................................................................................ 44
F
IGURE
28. T
HE
B
EHAVIOR OF THE
RPOS
AND
RCLK1 O
UTPUT
S
IGNALS
W
HILE THE
XRT73LC00A
IS
T
RANSMITTING
S
INGLE
-R
AIL
D
ATA
TO THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
....................................................................................................................... 44
4.0 DIAGNOSTIC FEATURES OF THE XRT73LC00A ............................................................................. 44
4.1 THE ANALOG LOCAL LOOP-BACK MODE ................................................................................................. 44
F
IGURE
29. T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK IN THE
XRT73LC00A ............................................................................................... 45
C
OMMAND
R
EGISTER
CR4 (A
DDRESS
= 0
X
04)............................................................................................. 45
4.2 THE DIGITAL LOCAL LOOP-BACK MODE .................................................................................................. 45
F
IGURE
30. T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK PATH IN THE
XRT73LC00A ....................................................................................... 46
C
OMMAND
R
EGISTER
CR4 (A
DDRESS
= 0
X
04)............................................................................................. 46
4.3 THE REMOTE LOOP-BACK MODE .............................................................................................................. 46
F
IGURE
31. T
HE
R
EMOTE
L
OOP
-B
ACK
P
ATH IN THE
XRT73LC00A................................................................................................. 47
C
OMMAND
R
EGISTER
CR4 (A
DDRESS
= 0
X
04)............................................................................................. 47
4.4 TXOFF FEATURES ........................................................................................................................................ 47
C
OMMAND
R
EGISTER
CR1 (A
DDRESS
= 0
X
01)............................................................................................. 48
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ........................................................................................... 48
F
IGURE
32. T
HE
XRT73LC00A E
MPLOYING THE
T
RANSMIT
D
RIVE
M
ONITOR
F
EATURES
................................................................. 48
F
IGURE
33. T
WO
LIU’
S
, E
ACH
M
ONITORING THE
T
RANSMIT
O
UTPUT
S
IGNAL OF THE
O
THER
LIU IC ............................................... 49
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE ........................................................................................... 49
C
OMMAND
R
EGISTER
CR1 (A
DDRESS
= 0
X
01)............................................................................................. 50
II