EP1S80B956C6N datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> EP1S80B956C6N

EP1S80B956C6N: DescriptionFPGA - Field Programmable Gate Array FPGA - Stratix I 7904 LABs 683 IOs; CategoryProgrammable logic devices Programmable logic; File Size10MB，864 Pages; ManufacturerAltera (Intel); Environmental Compliance

Download Datasheet Parametric View All

EP1S80B956C6N Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	EP1S80B956C6N	-	-	View	Buy Now

EP1S80B956C6N Overview

FPGA - Field Programmable Gate Array FPGA - Stratix I 7904 LABs 683 IOs

EP1S80B956C6N Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	BGA, BGA956,31X31,50
Contacts	956
Reach Compliance Code	compliant
ECCN code	3A001.A.7.A
Is Samacsys	N
JESD-30 code	S-PBGA-B956
JESD-609 code	e1
length	40 mm
Humidity sensitivity level	5A
Configurable number of logic blocks	9191
Number of entries	1238
Number of logical units	79040
Output times	1238
Number of terminals	956
Maximum operating temperature	85 °C
Minimum operating temperature
organize	9191 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA956,31X31,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	245
power supply	1.5,1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	40 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Stratix Device Handbook, Volume 1

101 Innovation Drive

San Jose, CA 95134

(408) 544-7000

http://www.altera.com

S5V1-3.4

Contents

Chapter Revision Dates .......................................................................... vii

About This Handbook .............................................................................. ix

How to Find Information ........................................................................................................................ ix

How to Contact Altera ............................................................................................................................. ix

Typographic Conventions ........................................................................................................................ x

Section I. Stratix Device Family Data Sheet

Revision History ............................................................................................................................ Part I–1

Chapter 1. Introduction

Introduction ............................................................................................................................................ 1–1

Features ................................................................................................................................................... 1–2

Chapter 2. Stratix Architecture

Functional Description .......................................................................................................................... 2–1

Logic Array Blocks ................................................................................................................................ 2–3

LAB Interconnects ............................................................................................................................ 2–4

LAB Control Signals ......................................................................................................................... 2–5

Logic Elements ....................................................................................................................................... 2–6

LUT Chain & Register Chain .......................................................................................................... 2–8

addnsub Signal ................................................................................................................................. 2–8

LE Operating Modes ........................................................................................................................ 2–8

Clear & Preset Logic Control ........................................................................................................ 2–13

MultiTrack Interconnect ..................................................................................................................... 2–14

TriMatrix Memory ............................................................................................................................... 2–21

Memory Modes ............................................................................................................................... 2–22

Clear Signals .................................................................................................................................... 2–24

Parity Bit Support ........................................................................................................................... 2–24

Shift Register Support .................................................................................................................... 2–25

Memory Block Size ......................................................................................................................... 2–26

Independent Clock Mode .............................................................................................................. 2–44

Input/Output Clock Mode ........................................................................................................... 2–46

Read/Write Clock Mode ............................................................................................................... 2–49

Single-Port Mode ............................................................................................................................ 2–51

Multiplier Block .............................................................................................................................. 2–57

Adder/Output Blocks ................................................................................................................... 2–61

Modes of Operation ....................................................................................................................... 2–64

Altera Corporation

iii

Contents

Stratix Device Handbook, Volume 1

DSP Block Interface ........................................................................................................................ 2–70

PLLs & Clock Networks ..................................................................................................................... 2–73

Global & Hierarchical Clocking ................................................................................................... 2–73

Enhanced & Fast PLLs ................................................................................................................... 2–81

Enhanced PLLs ............................................................................................................................... 2–87

Fast PLLs ........................................................................................................................................ 2–100

I/O Structure ...................................................................................................................................... 2–104

Double-Data Rate I/O Pins ......................................................................................................... 2–111

External RAM Interfacing ........................................................................................................... 2–115

Programmable Drive Strength ................................................................................................... 2–119

Open-Drain Output ...................................................................................................................... 2–120

Slew-Rate Control ........................................................................................................................ 2–120

Bus Hold ........................................................................................................................................ 2–121

Programmable Pull-Up Resistor ................................................................................................ 2–122

Advanced I/O Standard Support .............................................................................................. 2–122

Differential On-Chip Termination ............................................................................................. 2–127

MultiVolt I/O Interface ............................................................................................................... 2–129

High-Speed Differential I/O Support ............................................................................................ 2–130

Dedicated Circuitry ...................................................................................................................... 2–137

Byte Alignment ............................................................................................................................. 2–140

Power Sequencing & Hot Socketing ............................................................................................... 2–140

Chapter 3. Configuration & Testing

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3–1

SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5

Configuration ......................................................................................................................................... 3–5

Operating Modes .............................................................................................................................. 3–5

Configuring Stratix FPGAs with JRunner .................................................................................... 3–7

Configuration Schemes ................................................................................................................... 3–7

Partial Reconfiguration .................................................................................................................... 3–7

Remote Update Configuration Modes .......................................................................................... 3–8

Stratix Automated Single Event Upset (SEU) Detection ................................................................ 3–12

Custom-Built Circuitry .................................................................................................................. 3–13

Software Interface ........................................................................................................................... 3–13

Temperature Sensing Diode ............................................................................................................... 3–13

Chapter 4. DC & Switching Characteristics

Operating Conditions ........................................................................................................................... 4–1

Power Consumption ........................................................................................................................... 4–17

Timing Model ....................................................................................................................................... 4–19

Preliminary & Final Timing .......................................................................................................... 4–19

Performance .................................................................................................................................... 4–20

Internal Timing Parameters .......................................................................................................... 4–22

External Timing Parameters ......................................................................................................... 4–33

Stratix External I/O Timing .......................................................................................................... 4–36

I/O Timing Measurement Methodology .................................................................................... 4–60

External I/O Delay Parameters .................................................................................................... 4–66

Altera Corporation

Recommended Resources

Power circuit of LBO-522 dual trace oscilloscope

Class A FET amplifier power supply circuit diagram

STK0039 audio IC circuit diagram

Fan speed switch infrared remote control circuit-b

Power supply circuit diagram of CASPER 1489 monochrome display

820e computer motherboard circuit diagram_20

EEWORLD University Hall----Introduction to new power module products and their technical advantages: Introduction to new power module products and their technical advantages : https://training.eeworld.com.cn/course/4763...; hi5 Power technology

Advertising lights (using the meter-taking method): 1. Experimental task: Use the table method to make port P1 change a single light: move left 2 times, move right 2 times, and flash 2 times (delay time 0.2 seconds). 2. Circuit diagram　 3. Hardware con...; rain MCU

Common problems and solutions in CCS compilation: 1. warning: creating .stack section with default size of 400 (hex) words.This is because there is no set value for -stack in Project---Build Option---Linker. 2. warning: creating .sysmem section with ...; Jacktang Microcontroller MCU

C language pointer to array element: Pointers to array elements and operation rules The so-called pointers to array elements are essentially pointers to variables. Because each element in an array can actually be directly regarded as a v...; Aguilera Microcontroller MCU

Share the software phase-locking tutorial of C2000's 2812: [size=4]1. Phase lock[/size] [size=4] The meaning of phase lock is the automatic control of phase synchronization. The automatic control closed-loop system that can complete the phase synchronization ...; Aguilera DSP and ARM Processors

UCGUI drop-down box problem: As shown in the picture, there is a drop-down list control on the right side of the settings button, showing an arrow. I displayed the program as shown in the picture, which is very short.How to make ...; chenbingjy Embedded System

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components