EPM3512AFC256-7N datasheet, PDF

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EPM3512AFC256-7N: DescriptionCPLD - Complex Programmable Logic Devices CPLD - MAX 3000A 512 Macro 208 IOs; CategoryProgrammable logic devices Programmable logic; File Size709KB，46 Pages; ManufacturerAltera (Intel); Environmental Compliance

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EPM3512AFC256-7N Overview

CPLD - Complex Programmable Logic Devices CPLD - MAX 3000A 512 Macro 208 IOs

EPM3512AFC256-7N Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	FINE LINE, BGA-256
Contacts	256
Reach Compliance Code	unknown
ECCN code	3A991
Is Samacsys	N
Other features	YES
In-system programmable	YES
JESD-30 code	S-PBGA-B256
JESD-609 code	e1
JTAG BST	YES
length	17 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	208
Number of macro cells	512
Number of terminals	256
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 208 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3,3.3 V
Programmable logic type	EE PLD
propagation delay	7.5 ns
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	17 mm
Base Number Matches	1

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MAX 3000A

Programmable Logic

Device Family

Data Sheet

June 2006, ver. 3.5

Features...

■

High–performance, low–cost CMOS EEPROM–based programmable

logic devices (PLDs) built on a MAX

architecture (see

Table 1)

3.3-V in-system programmability (ISP) through the built–in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with

advanced pin-locking capability

–

ISP circuitry compliant with IEEE Std. 1532

Built–in boundary-scan test (BST) circuitry compliant with

IEEE Std. 1149.1-1990

Enhanced ISP features:

–

Enhanced ISP algorithm for faster programming

–

ISP_Done bit to ensure complete programming

–

Pull-up resistor on I/O pins during in–system programming

High–density PLDs ranging from 600 to 10,000 usable gates

4.5–ns pin–to–pin logic delays with counter frequencies of up to

227.3 MHz

MultiVolt

I/O interface enabling the device core to run at 3.3 V,

while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic

levels

Pin counts ranging from 44 to 256 in a variety of thin quad flat pack

(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier

(PLCC), and FineLine BGA

packages

Hot–socketing support

Programmable interconnect array (PIA) continuous routing structure

for fast, predictable performance

Industrial temperature range

Table 1. MAX 3000A Device Features

Feature

Usable gates

Macrocells

Logic array blocks

Maximum user I/O

pins

(ns)

CO1

(ns)

CNT

(MHz)

Altera Corporation

DS-MAX3000A-3.5

EPM3032A

600

4.5

2.9

3.0

227.3

EPM3064A

1,250

4.5

2.8

3.1

222.2

EPM3128A

2,500

128

5.0

3.3

3.4

192.3

EPM3256A

5,000

256

161

7.5

5.2

4.8

126.6

EPM3512A

10,000

512

208

7.5

5.6

4.7

116.3

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