MC100EPT25D datasheet, PDF - EEWORLD Datasheet

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MC100EPT25D: DescriptionTranslation - Voltage Levels Diff LVECL/ECL; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size127KB，8 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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MC100EPT25D Overview

Translation - Voltage Levels Diff LVECL/ECL

MC100EPT25D Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ON Semiconductor
Parts packaging code	SOIC
package instruction	SOIC-8
Contacts	8
Reach Compliance Code	not_compliant
ECCN code	EAR99
Factory Lead Time	1 week
Other features	LVECL TO ECL TRANSALATION ALSO POSSIBLE
maximum delay	1.6 ns
Interface integrated circuit type	ECL TO TTL TRANSLATOR
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Nominal negative supply voltage	-3.3 V
Number of digits	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	TOTEM-POLE
Output latch or register	NONE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240
power supply	-4.5 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	ECL
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn80Pb20)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
Base Number Matches	1

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MC100EPT25

-3.3V / -5V Differential ECL

to +3.3V LVTTL Translator

Description

The MC100EPT25 is a Differential ECL to LVTTL translator. This

device requires +3.3 V,

−3.3

V to

−5.2

V, and ground. The small

outline 8−lead package and the single gate of the EPT25 make it ideal

for applications which require the translation of a clock or data signal.

The V

output allows the EPT25 to also be used in a single−ended

input mode. In this mode the V

output is tied to the D input for a

inverting buffer or the D input for a non−inverting buffer. If used, the

pin should be bypassed to ground with at least a 0.01

capacitor.

Features

http://onsemi.com

MARKING DIAGRAMS*

SOIC−8

D SUFFIX

CASE 751

KPT25

ALYW

•

1.1 ns Typical Propagation Delay

•

Maximum Frequency > 275 MHz Typical

•

Operating Range: V

= 3.0 V to 3.6 V;

•

TSSOP−8

DT SUFFIX

CASE 948R

KA25

ALYWG

−5.5

V to

−3.0

V; GND = 0 V

24 mA TTL Outputs

Q Output Will Default LOW with Inputs Open or at V

Output

Open Input Default State

Safety Clamp on Inputs

Pb−Free Packages are Available

DFN8

MN SUFFIX

CASE 506AA

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Date Code

= Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

Semiconductor Components Industries, LLC, 2008

August, 2008

−

Rev. 16

Publication Order Number:

MC100EPT25/D

3V MG

MC100EPT25D Related Products

	MC100EPT25D	MC100EPT25DR2	MC100EPT25DT
Description	Translation - Voltage Levels Diff LVECL/ECL	Translation - Voltage Levels Diff LVECL/ECL	Translation - Voltage Levels Diff LVECL/ECL
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	ON Semiconductor	ON Semiconductor	ON Semiconductor
Parts packaging code	SOIC	SOIC	SOIC
package instruction	SOIC-8	SOIC-8	PLASTIC, TSSOP-8
Contacts	8	8	8
Reach Compliance Code	not_compliant	not_compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99
Other features	LVECL TO ECL TRANSALATION ALSO POSSIBLE	LVECL TO ECL TRANSALATION ALSO POSSIBLE	LVECL TO ECL TRANSALATION ALSO POSSIBLE
maximum delay	1.6 ns	1.6 ns	1.6 ns
Interface integrated circuit type	ECL TO TTL TRANSLATOR	ECL TO TTL TRANSLATOR	ECL TO TTL TRANSLATOR
JESD-30 code	R-PDSO-G8	R-PDSO-G8	S-PDSO-G8
JESD-609 code	e0	e0	e0
length	4.9 mm	4.9 mm	3 mm
Nominal negative supply voltage	-3.3 V	-3.3 V	-3.3 V
Number of digits	1	1	1
Number of functions	1	1	1
Number of terminals	8	8	8
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Output characteristics	TOTEM-POLE	TOTEM-POLE	TOTEM-POLE
Output latch or register	NONE	NONE	NONE
Output polarity	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	TSSOP
Encapsulate equivalent code	SOP8,.25	SOP8,.25	TSSOP8,.19
Package shape	RECTANGULAR	RECTANGULAR	SQUARE
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240	240	240
power supply	-4.5 V	-4.5 V	-4.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	1.75 mm	1.1 mm
Maximum supply voltage	3.6 V	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	ECL	ECL	ECL
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn80Pb20)	Tin/Lead (Sn80Pb20)	Tin/Lead (Sn90Pb10)
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30
width	3.9 mm	3.9 mm	3 mm
Base Number Matches	1	1	1
Factory Lead Time	1 week	-	1 week

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