MC100EPT25
-3.3V / -5V Differential ECL
to +3.3V LVTTL Translator
Description
The MC100EPT25 is a Differential ECL to LVTTL translator. This
device requires +3.3 V,
−3.3
V to
−5.2
V, and ground. The small
outline 8−lead package and the single gate of the EPT25 make it ideal
for applications which require the translation of a clock or data signal.
The V
BB
output allows the EPT25 to also be used in a single−ended
input mode. In this mode the V
BB
output is tied to the D input for a
inverting buffer or the D input for a non−inverting buffer. If used, the
V
BB
pin should be bypassed to ground with at least a 0.01
mF
capacitor.
Features
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MARKING DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
KPT25
ALYW
G
•
1.1 ns Typical Propagation Delay
•
Maximum Frequency > 275 MHz Typical
•
Operating Range: V
CC
= 3.0 V to 3.6 V;
•
•
•
•
•
•
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
KA25
ALYWG
G
V
EE
=
−5.5
V to
−3.0
V; GND = 0 V
24 mA TTL Outputs
Q Output Will Default LOW with Inputs Open or at V
EE
V
BB
Output
Open Input Default State
Safety Clamp on Inputs
Pb−Free Packages are Available
1
DFN8
MN SUFFIX
CASE 506AA
A
L
Y
W
M
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
August, 2008
−
Rev. 16
1
Publication Order Number:
MC100EPT25/D
3V MG
G
4
MC100EPT25
Table 1. PIN DESCRIPTION
V
EE
1
8
V
CC
PIN
Q
D
2
LVTTL
7
Q
D*, D*
V
CC
V
BB
D
3
LVECL/ECL
6
NC
GND
V
EE
NC
V
BB
4
5
GND
EP
FUNCTION
LVTTL Output
Differential ECL Input Pair
Positive Supply
Output Reference Voltage
Ground
Negative Supply
No Connect
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
Figure 1. 8−Lead Pinout
(Top View)
and Logic Diagram
* Pins will default LOW when left open.
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
Level 1
Level 1
Level 1
Value
75 kW
N/A
> 4 kV
> 200 V
> 2 kV
Pb−Free Pkg
Level 1
Level 3
Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
UL−94 V−0 @ 0.125 in
111 Devices
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2
MC100EPT25
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
IN
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
Parameter
Positive Power Supply
Negative Power Supply
Input Voltage
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
(Note 2)
DFN8
8 SOIC
8 SOIC
8 SOIC
8 TSSOP
8 TSSOP
8 TSSOP
DFN8
DFN8
Condition 1
GND = 0 V
GND = 0 V
GND = 0 V
Condition 2
V
EE
=
−5.0
V
V
CC
= +3.3 V
Rating
3.8
−6
0 to V
EE
±
0.5
−40
to +85
−65
to +150
190
130
41 to 44
185
140
41 to 44
129
84
265
265
35 to 40
Unit
V
V
V
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
°C/W
Thermal Resistance (Junction−to−Case)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power)
Table 4. NECL DC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
=
−5.5
V to
−3.0
V; GND = 0.0 V (Note 3)
−40°C
Symbol
IEE
25°C
Max
25
−880
−1625
Min
8.0
−1225
−1945
−1525
−1425
Typ
16
Max
25
−880
−1625
−1325
0.0
150
0.5
0.5
Min
8.0
−1225
−1945
−1525
85°C
Typ
16
Max
25
−880
−1625
−1425
−1325
0.0
150
Unit
mA
mV
mV
mV
V
mA
mA
Characteristic
Power Supply Current
Input HIGH Voltage Single−Ended
Input LOW Voltage Single−Ended
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Note 4)
Input HIGH Current
Input LOW Current
Min
8.0
−1225
−1945
−1525
Typ
16
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
−1425
−1325
0.0
150
V
EE
+ 2.0
V
EE
+ 2.0
V
EE
+ 2.0
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input parameters vary 1:1 with GND.
4. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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3
MC100EPT25
Table 5. TTL OUTPUT DC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
=
−5.5
V to
−3.0
V; GND = 0.0 V; T
A
=
−40°C
to 85°C
Symbol
V
OH
V
OL
I
CCH
I
CCL
Characteristic
Output HIGH Voltage
Output LOW Voltage
Power Supply Current
Power Supply Current
Condition
I
OH
=
−3.0
mA
I
OL
= 24 mA
6
7
10
12
Min
2.2
0.5
14
17
Typ
Max
Unit
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V; V
EE
=
−5.5
V to
−3.0
V; GND = 0.0 V (Note 5)
−40°C
Symbol
f
max
t
PLH
, t
PHL
t
SKPP
t
JITTER
V
PP
t
r
t
f
Characteristic
Maximum Frequency
(See Figure 2 F
max
/JITTER)
Propagation Delay to Output Differential
(Cross−Point to 1.5 V)
Device−to−Device Skew (Note 6)
Random Clock Jitter (RMS)
(See Figure 2 F
max
/JITTER)
Input Voltage Swing (Differential)
Output Rise/Fall Times
(0.8 V
−
2.0 V)
Q, Q
150
300
900
0.2
800
474
1160
Min
275
500
950
1300
500
<1
1200
600
1400
150
300
900
0.2
800
459
1100
Typ
Max
Min
275
800
950
1600
500
<1
1200
600
1400
150
300
900
0.2
800
457
1100
25°C
Typ
Max
Min
275
800
960
1600
500
<1
1200
600
1400
85°C
Typ
Max
Unit
MHz
ps
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured with a 750 mV 50% duty−cycle clock source. R
L
= 500
W
to GND and C
L
= 20 pF to GND. Refer to Figure 3.
6. Skews are measured between outputs under identical conditions.
2800
2400
2000
1600
1200
V
OL
0.5 V
800
400
0
(JITTER)
V
OH
7
6
5
4
3
2
V
OUTpp
(mV)
1
25
100
175
250
325
400
475
550
625
FREQUENCY (MHz)
Figure 2. F
max
/Jitter
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4
JITTER
OUT
ps (RMS)
É
É
É
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
MC100EPT25
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*C
L
includes
fixture
capacitance
C
L
*
R
L
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used for Device Evaluation
ORDERING INFORMATION
Device
MC100EPT25D
MC100EPT25DG
MC100EPT25DR2
MC100EPT25DR2G
MC100EPT25DT
MC100EPT25DTG
MC100EPT25DTR2
MC100EPT25DTR2G
MC100EPT25MNR4
MC100EPT25MNR4G
Package
SOIC−8
SOIC−8
(Pb−Free)
SOIC−8
SOIC−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
DFN8
DFN8
(Pb−Free)
Shipping
†
98 Units / Rail
98 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
100 Units / Rail
100 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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