QL3025 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > QL3025

Preview

QL3025: Description25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density; File Size179KB，17 Pages; ManufacturerETC

Download Datasheet View All

QL3025 Overview

25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QL3025 Preview

QL3025 pASIC 3 FPGA Data Sheet

••••••

25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance

and High Density

Device Highlights

High Performance & High Density

•

25,000 Usable PLD Gates with 204 I/Os

•

300 MHz 16-bit Counters,

Four Low-Skew Distributed

Networks

•

Two array clock/control networks available

400 MHz Datapaths

•

0.35

µm

four-layer metal non-volatile

CMOS process for smallest die sizes

Easy to Use / Fast Development

Cycles

•

100% routable with 100% utilization and

to the logic cell flip-flop clock, set and reset

inputs — each driven by an input-only pin

•

Two global clock/control networks available

to the logic cell; F1, clock set, reset inputs

and the input, I/O register clock, reset, and

enable inputs as well as the output enable

control — each driven by an input-only or

I/O pin, or any logic cell output or I/O cell

feedback

complete pin-out stability

•

Variable-grain logic cells provide high

performance and 100% utilization

•

Comprehensive design tools include high

quality Verilog/VHDL synthesis

High Performance

•

Input + logic cell + output total delays

under 6 ns

•

Data path speeds over 400 MHz

•

Counter speeds over 300 MHz

Advanced I/O Capabilities

•

Interfaces with both 3.3 V and 5.0 V devices

•

PCI compliant with 3.3 V and 5.0 V buses

for -1/-2/-3/-4 speed grades

•

Full JTAG boundary scan

•

I/O Cells with individually controlled

Registered Input Path and Output Enables

Total of 204 I/O Pins

•

196 bidirectional input/output pins,

PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

•

Four High Drive input-only pins

•

Four High Drive input-only/distributed

network pins

Figure 1: 672 pASIC 3 Logic Cells

www.quicklogic.com

•

QL3025 pASIC 3 FPGA Data Sheet Rev E

Architecture Overview

The QL3025 is a 25,000 usable PLD gate member of the pASIC 3 family of FPGAs.

pASIC 3 FPGAs are fabricated on a 0.35

µm

four-layer metal process using QuickLogic



patented ViaLink



technology to provide a unique combination of high performance, high

density, low cost, and extreme ease-of-use.

The QL3025 contains 672 logic cells. With a maximum of 204 I/Os, the QL3025 is

available in

144-pin TQFP, 208-pin PQFP, and 256-pin PBGA packages.

Software support for the complete pASIC 3 family, including the QL3025, is available

through three basic packages. The turnkey QuickWorks



package provides the most

complete FPGA software solution from design entry to logic synthesis, to place and route,

to simulation. The QuickTools

for Workstations package provides a solution for designers

who use Cadence



, Exemplar

, Mentor



, Synopsys



, Synplicity



, Viewlogic

, Aldec

or other third-party tools for design entry, synthesis, or simulation.

•

www.quicklogic.com

•

QL3025 pASIC 3 FPGA Data Sheet Rev E

Electrical Specifications

AC Characteristics at V

= 3.3 V, TA = 25°C (K = 1.00)

To calculate delays, multiply the appropriate K factor from

Table 7

by the numbers provided

Table 1

through

Table 5

Table 1: Logic Cells

Symbol

Parameter

CLK

CWHI

CWLO

SET

RESET

Combinatorial Delay

Setup Time

Hold Time

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

Reset Delay

Set Width

Reset Width

Propagation Delays (ns) Fanout

1.7

0.0

1.0

1.2

1.3

1.1

1.9

1.8

1.9

1.7

0.0

1.2

1.5

1.3

1.9

1.8

2.2

1.7

0.0

1.5

1.2

1.8

1.6

1.9

1.8

3.2

1.7

0.0

2.5

1.2

2.8

2.6

1.9

1.8

1.4

1.7

0.0

0.7

1.2

1.0

0.8

1.9

1.8

a. Stated timing for worst case Propagation Delay over process variation at V

= 3.3 V and

TA = 25

C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature

settings as specified in

Table 7

b. These limits are derived from a representative selection of the slowest paths through the

pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should

be determined from timing analysis of your particular design.

Table 2: Input-Only/Clock Cells

Symbol

Parameter

INI

ISU

lCLK

lRST

lESU

lEH

High Drive Input Delay

High Drive Input, Inverting Delay

Input Register Set-Up Time

Input Register Hold Time

Input Register Clock To Q

Input Register Reset Delay

Input Register clock Enable Set-Up Time

Input Register Clock Enable Hold Time

1.5

1.6

3.1

0.0

0.7

0.6

2.3

0.0

Propagation Delays (ns) Fanout

1.6

1.7

3.1

0.0

0.8

0.7

2.3

0.0

1.8

1.9

3.1

0.0

1.0

0.9

2.3

0.0

1.9

2.0

3.1

0.0

1.1

1.0

2.3

0.0

2.4

2.5

3.1

0.0

1.6

1.5

2.3

0.0

2.9

3.0

3.1

0.0

2.1

2.0

2.3

0.0

4.4

4.5

3.1

0.0

3.6

3.5

2.3

0.0

a. Stated timing for worst case Propagation Delay over process variation at V

= 3.3 V and

TA = 25

C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and tempera-

ture settings as specified in

Table 7

www.quicklogic.com

•

QL3025 pASIC 3 FPGA Data Sheet Rev E

Table 3: Clock Cells

Symbol

Parameter

Propagation Delays (ns) Loads per Half Column

ACK

GCKP

GCKB

Array Clock Delay

Global Clock Pin Delay

Global Clock Buffer Delay

1.2

0.7

0.8

1.2

0.7

0.8

1.3

0.7

0.9

1.3

0.7

0.9

1.5

0.7

1.1

1.6

0.7

1.2

1.7

0.7

1.3

a. The array distributed networks consist of 40 half columns and the global distributed networks con-

sist of 44 half columns, each driven by an independent buffer. The number of half columns used

does not affect clock buffer delay. The array clock has up to eight loads per half column. The glo-

bal clock has up to 11 loads per half column.

Table 4: Input-Only I/O Cells

Symbol

Parameter

Propagation Delays (ns) Fanout

I/O

ISU

lOCLK

lORST

lESU

lEH

Input Delay (bidirectional pad)

Input Register Set-Up Time

Input Register Hold Time

Input Register Clock To Q

Input Register Reset Delay

Input Register clock Enable Set-Up Time

Input Register Clock Enable Hold Time

1.3

3.1

0.0

0.7

0.6

2.3

0.0

1.6

3.1

0.0

1.0

0.9

2.3

0.0

1.8

3.1

0.0

1.2

1.1

2.3

0.0

2.1

3.1

0.0

1.5

1.4

2.3

0.0

3.1

0.0

2.5

2.4

2.3

0.0

3.6

3.1

0.0

3.0

2.9

2.3

0.0

a. Stated timing for worst case Propagation Delay over process variation at V

= 3.3 V and

TA = 25

C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature

settings as specified in

Table 7

•

www.quicklogic.com

•

QL3025 pASIC 3 FPGA Data Sheet Rev E

Table 5: Output-Only I/O Cells

Symbol

Parameter

OUTLH

OUTHL

PZH

PZL

PHZ

PLZ

Output Delay Low to High

Output Delay High to Low

Output Delay Tri-state to High

Output Delay Tri-state to Low

Output Delay High to Tri-State

Output Delay Low to Tri-State

Propagation Delays (ns) Output Load

Capacitance (pF)

2.5

2.6

1.7

2.0

3.1

3.2

2.2

2.6

100

3.6

3.7

2.8

3.1

150

4.7

4.8

3.9

4.2

2.1

2.2

1.2

1.6

2.0

1.2

a. The following loads presented in

Figure 2

are used for t

PXZ

PHZ

1ΚΩ

5 pF

1ΚΩ

PLZ

5 pF

Figure 2: Loads used for t

PXZ

www.quicklogic.com

•

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

Recommended Resources

Three-phase zero-voltage switching circuit using CA3058 zero-trigger integrated circuit

Food spoilage measuring instrument circuit

T4163A single column coordinate boring machine electrical schematic circuit (1)

Combustible gas leak monitoring and alarm circuit

DM type electric cat circuit

General-Purpose Power supply circuit

President of the Chinese Academy of Sciences: Turn the US bottleneck list into a scientific research list: "We have turned the US's choke point list into our scientific research task list, such as bearing steel, lithography machines, and some key core technologies. We will strive to focus on the major area...; eric_wang Talking

Siemens Industrial Automation Data Collection (August 9, 2019): Siemens Industrial Automation Data Collection (August 9, 2019) Download address: http://www.ad.siemens.com.cn/service/download/documentlist.pdf...; osdocument Download Centre

The troubles of capacitor testers in traditional mode - Part 1: This content is originally created by Uncle Hai , a user on the EEWORLD forum. If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source In...; 海大叔 Talking

Playing with Zynq Serial 19——[ex02] A happy running water lamp based on Zynq PL: 1. Function OverviewZstar 's Zynq PL is connected to 3 LED indicators. As shown in the figure, the 3 LED indicators are connected in series with a 510 ohm current limiting resistor at the positive pol...; ove学习使我快乐 FPGA/CPLD

5G O-RAN All-in-one Small Base Station Hardware White Box Reference Architecture: The hardware white-boxization of O-RAN needs to go through five stages, and this article focuses on the third stage. Phase 1: Based on general-purpose computer hardware Phase 2: Dedicated daughter car...; 兰博 RF/Wirelessly

[Problem Feedback] Problem with the "SplitContainer" control of Anlu TangDynastyr.: I originally raised the message box at the bottom to see the warning message, but I tried many times to adjust it back but failed. Sometimes it didn't respond, and sometimes the window was separated. ...; littleshrimp Domestic Chip Exchange

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components