DS90UB964-Q1 datasheet, PDF - EEWORLD Datasheet

DS90UB964-Q1: DescriptionDS90UB964-Q1 Quad 1MP Camera Hub FPD-Link III Deserializer With Dual CSI-2 Output Ports for 1MP Cameras; Categorysemiconductor Analog mixed-signal IC; File Size3MB，117 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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DS90UB964-Q1 Overview

DS90UB964-Q1 Quad 1MP Camera Hub FPD-Link III Deserializer With Dual CSI-2 Output Ports for 1MP Cameras

Parameter Name	Attribute value
Approx. price(US$)	15.00 \| 1ku
Color depth(bpp)	12
Input compatibility	FPD-Link III LVDS
Operating temperature range(C)	-40 to 105
Diagnostics	BIST
Function	Deserializer
Rating	Automotive
Pixel clock min(MHz)	25
Output compatibility	MIPI CSI-2
Signal conditioning	Adaptive Equalizer,Programmable Equalizer
Pixel clock(Max)(MHz)	100
Package Group	VQFN\|64
Total throughput(Mbps)	13312
EMI reduction	LVDS
Features	CRC,Coax or STP,Flexible GPIOs,Pattern Generation,Internal Programmable Precision Frame Sync Generator,Port Replication Mode

	DS90UB964-Q1	DS90UB964TRGCTQ1	DS90UB964TRGCRQ1	DS90UB964
Description	DS90UB964-Q1 Quad 1MP Camera Hub FPD-Link III Deserializer With Dual CSI-2 Output Ports for 1MP Cameras	Quad 1MP Camera Hub FPD-Link III Deserializer With Dual CSI-2 Output Ports for 1MP Cameras 64-VQFN -40 to 105	Quad 1MP Camera Hub FPD-Link III Deserializer With Dual CSI-2 Output Ports for 1MP Cameras 64-VQFN -40 to 105	FPD-Link III 1 Megapixel Camera Hub Deserializer
Approx. price(US$)	15.00 \| 1ku	15.00 \| 1ku	15.00 \| 1ku	-
Color depth(bpp)	12	12	12	-
Input compatibility	FPD-Link III LVDS	FPD-Link III LVDS	FPD-Link III LVDS	-
Operating temperature range(C)	-40 to 105	-40 to 105	-40 to 105	-
Diagnostics	BIST	BIST	BIST	-
Function	Deserializer	Deserializer	Deserializer	-
Rating	Automotive	Automotive	Automotive	-
Pixel clock min(MHz)	25	25	25	-
Output compatibility	MIPI CSI-2	MIPI CSI-2	MIPI CSI-2	-
Signal conditioning	Adaptive Equalizer,Programmable Equalizer	Adaptive Equalizer,Programmable Equalizer	Adaptive Equalizer,Programmable Equalizer	-
Pixel clock(Max)(MHz)	100	100	100	-
Package Group	VQFN\|64	VQFN\|64	VQFN\|64	-
Total throughput(Mbps)	13312	13312	13312	-
EMI reduction	LVDS	LVDS	LVDS	-
Features	CRC,Coax or STP,Flexible GPIOs,Pattern Generation,Internal Programmable Precision Frame Sync Generator,Port Replication Mode	CRC,Coax or STP,Flexible GPIOs,Pattern Generation,Internal Programmable Precision Frame Sync Generator,Port Replication Mode	CRC,Coax or STP,Flexible GPIOs,Pattern Generation,Internal Programmable Precision Frame Sync Generator,Port Replication Mode	-

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