Advance Information
Pin Descriptions
Terminal
Name
Description
Analog Ground
Analog power
Clock input with a (10K-100K Ohm) pulldown resistor
Complentary clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Complementary feedback clock input
Feedback clock output
Complementary feedback clock output
Output Enable (Asynchronous)
Output Select (tied to GND or V
000
)
Ground
Logic and output power
Clock outputs
Complementary clock outputs
No ball
Electrical
Characteristics
Ground
1.8 V nominal
Differential input
Differential input
Differential input
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
1.8V nominal
Differential outputs
Differential outputs
ICS97U870
AGND
AV
DD
CLK_INT
CLK_INC
FB_INT
FB_INC
FB_OUTT
FB_OUTC
OE
OS
GND
V
DD
Q
CLKT[0:9]
CLKC[0:9]
NB
The PLL clock buffer,
ICS97U870,
is designed for aVooa of 1.8 V, a AVoo of 1.8V and differential data input and output
levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97U870
is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:91) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC).
The clock outputs are controlled by the input clocks(CLK_INT, CLK_INC), the feedback clocks(FB_INT, FB_INC), the
LVCMOS program pins(OE, OS) and the Analog Power input(AVDD). When OE is low, the outputs(except FB_OUTT/
FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a
program pin that must be tied to GND orVooa. When OS is high, OE will function as described above. When OS is low,
OE has no effect on CLKT7/CLKC7(they are free running in addition to FB_OUTT/FB_OUTC). When AVoo is grounded,
the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair(FB_INT, FB_INC) and the input clock pair(CLK_INT, CLK_INC)
within the specified stabilization time tsrAB,
The PLL in
ICS97U870
clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks(CLKT[0:9], CLKC[0:9]).
ICS97U870
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97U870
is characterized for operation from 0
°
C to 70
°
C.
0817---07/07/03
2
Advance Information
ICS97U870
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) ......... -0.5V to 2.5V
Logic Inputs ......................... GND - 0.5V to Vooa +0.5V
Ambient Operating Temperature .......... 0
°
C to+70
°
C
Storage Temperature ................... -65
°
C to+1 50
°
C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.T hese
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied.Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
0 - 70
°
C; Supply Voltage AVDDQ, VDDQ
=
1.8 V +/- 0.1V {unless otherwise stated)
MIN
PARAMET ER
SYMBOL
CONDITIONS
T YP
Input High Current
,
V
1 =
V
00
0 or GND
l
1
H
\v('
►
(CLK INT , CLK INC)
Input Low Current (OE,
V
1 =
V
00
0 or GND
l
1L
/
OS, FB INT , FB INC)
Output Disabled Low
loo
L
OE
=
L, Voo
L =
100mV
100
Current
-
Operating Supply
C
L =
0pf@ 2 70MHz
1
001
.8
,
½'
'>
Current
C
L =
0pf
loo
L
o
_s:_½
TA
=
..
MAX
±250
±10
UNIT S
µA
µA
µA
vv
300
500
- 1.2
mA
µA
V
V
V
V
V
pF
pF
Input Clamp Voltage
High-level output
voltage
V
1
K
VoH
Vo
L
C
1
N
CouT
Low-level output voltage
Input Capacitance
1
Output Capacitance
1
Vooa
=
1.7V lin
loH
=
- 100 µA
loH
=
-9 mA
lo
L=
100 µA
=
- 1 8mA
Vooa - 0.2
1.1
UJ
V
lo
L=
9 mA
VI
=
GND or Vooa
=
r;½
/
/
,
_,, I
,
1.45
0.25
0.10
0.6
3
3
VoUT
GND or Vooa
'Guaranteed by design, not 100% tested in production.
½'7
2
2
A½
½
0817---07/07/03
}s½
'
,
Y
<
4
T
A=
0 - 70
°
C; Supply Voltage AVDD,VDDQ
=
1.8 V
+/-
0.1V (unless otherwise stated)
TYP
MAX
UNITS
PARAMETER
SYMBOL
CONDITIONS
MIN
1.9
1.8
V
1.7
Supply Voltage
VDoo, AvDD
CLK_INT, CLK_INC, FB_INC,
0.35
X
VDoo
V
Low level input voltage
V1L
FB INT
0.35 x VDDQ
V
OE,OS
CLK_INT,CLK_INC universal
Low level universal input
VDoo - 0.4
V
0.4
V1L
input mode
voltage
CLK_INT, CLK_INC, FB_INC,
0.65
X
VDDQ
V
High level input voltage
FB INT
V1H
OE,OS
0.65
X
VDDo
V
High level universal input
CLK_INT,CLK_INC universal
V1H
0.8
VDDQ
+
0.3
V
voltage
input mode
)
'-..:::
/
DC input signal voltage
-0.3
V1N
VDoo
+
0.3
V
(note 2)
½
DC - CLK_INT,CLK_INC,
0.3
VDoo
+
0.4
V
Differential input signal
FB INC, FB INT
VID
'
voltage (note 3)
AC - CLK_INT,CLK_INC,
0.6
VDoo
+
0.4
V
FB INC, FB INT
Output differential cross-
V
Vox
VDoo/2 - 0.10
VDoo/2
+
0.10
<.
1..---...
voltaae (note 4)
,,.
Input differential cross-
I
Universal input mode
Vix
voltaqe (note 4)
("
0.45 (V1H - V1L) Vm:12 0.55 (V1H - V1L V
High level output current
loH
mA
-9
(,
V
½ '-..:;:::::.
V
f( \
Low level output current
loL
9
mA
Operating free-air
T
A
0
70
oc
/4')\.
temperature
½
Advance Information
ICS97U870
Recommended Operating Condition
(see note1)
-
-./
.½
f
,l
""
'v
½<'
/
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of Vooa and is the
voltage at which the differential signal must be crossing.
0817--07/07/03
5