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HY57V161610DTC-6

Description
1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50
Categorystorage    storage   
File Size174KB,13 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Download Datasheet Parametric Compare View All

HY57V161610DTC-6 Overview

1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50

HY57V161610DTC-6 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSK Hynix
Parts packaging codeTSOP2
package instructionTSOP2, TSOP50,.46,32
Contacts50
Reach Compliance Codeunknow
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time5.5 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)167 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G50
length20.968 mm
memory density16777216 bi
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals50
word count1048576 words
character code1000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize1MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP50,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.001 A
Maximum slew rate0.12 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
HY57V161610D
2 Banks x 512K x 16 Bit Synchronous DRAM
DESCRIPTION
THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic
applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initi-
ated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A
burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a
new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)
FEATURES
Single 3.0V to 3.6V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by UDQM/LDQM
Internal two banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 1, 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY57V161610DTC-5
HY57V161610DTC-55
HY57V161610DTC-6
HY57V161610DTC-7
HY57V161610DTC-8
HY57V161610DTC-10
HY57V161610DTC-15
Clock Frequency
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
66MHz
Organization
Interface
Package
2Banks x 512Kbits x 16
LVTTL
400mil
50pin TSOP II
Note :
1. V
DD
(min) of HY57V161610DTC-5/55 is 3.15V
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for
use of circuits described. No patent licenses are implied
Rev. 4.0/Aug. 02
1

HY57V161610DTC-6 Related Products

HY57V161610DTC-6 HY57V161610DTC-10 HY57V161610DTC-15 HY57V161610D
Description 1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50 1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50 1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50 1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50
memory width 16 16 16 16
Number of functions 1 1 1 1
Number of ports 1 1 1 1
Number of terminals 50 50 50 50
Maximum operating temperature 70 °C 70 °C 70 °C 70 Cel
organize 1MX16 1MX16 1MX16 1M × 16
surface mount YES YES YES Yes
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL pair
Maker SK Hynix SK Hynix SK Hynix -
Parts packaging code TSOP2 TSOP2 TSOP2 -
package instruction TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32 TSOP2, -
Contacts 50 50 50 -
Reach Compliance Code unknow unknow unknow -
ECCN code EAR99 EAR99 EAR99 -
access mode DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST -
Maximum access time 5.5 ns 7 ns 7 ns -
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH -
JESD-30 code R-PDSO-G50 R-PDSO-G50 R-PDSO-G50 -
length 20.968 mm 20.968 mm 20.968 mm -
memory density 16777216 bi 16777216 bi 16777216 bi -
Memory IC Type SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM -
word count 1048576 words 1048576 words 1048576 words -
character code 1000000 1000000 1000000 -
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code TSOP2 TSOP2 TSOP2 -
Package shape RECTANGULAR RECTANGULAR RECTANGULAR -
Package form SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE -
Certification status Not Qualified Not Qualified Not Qualified -
Maximum seat height 1.2 mm 1.2 mm 1.2 mm -
self refresh YES YES YES -
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V -
Minimum supply voltage (Vsup) 3 V 3 V 3 V -
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V -
technology CMOS CMOS CMOS -
Terminal pitch 0.8 mm 0.8 mm 0.8 mm -
width 10.16 mm 10.16 mm 10.16 mm -

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