HY57V161610DTC-10 datasheet, PDF

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HY57V161610DTC-10: Description1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50; Categorystorage storage; File Size174KB，13 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V161610DTC-10 Overview

1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50

HY57V161610DTC-10 Parametric

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP50,.46,32
Contacts	50
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G50
JESD-609 code	e6
length	20.968 mm
memory density	16777216 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	50
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP50,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.11 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

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HY57V161610D

2 Banks x 512K x 16 Bit Synchronous DRAM

DESCRIPTION

THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic

applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16.

HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized

with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initi-

ated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A

burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a

new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.0V to 3.6V power supply

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin

pitch

All inputs and outputs referenced to positive edge of system

clock

Data mask function by UDQM/LDQM

Internal two banks operation

•

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequence Burst

- 1, 2, 4 and 8 for Interleave Burst

Programmable CAS Latency ; 1, 2, 3 Clocks

ORDERING INFORMATION

Part No.

HY57V161610DTC-5

HY57V161610DTC-55

HY57V161610DTC-6

HY57V161610DTC-7

HY57V161610DTC-8

HY57V161610DTC-10

HY57V161610DTC-15

Clock Frequency

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

66MHz

Organization

Interface

Package

2Banks x 512Kbits x 16

LVTTL

400mil

50pin TSOP II

Note :

1. V

(min) of HY57V161610DTC-5/55 is 3.15V

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for

use of circuits described. No patent licenses are implied

Rev. 4.0/Aug. 02

HY57V161610DTC-10 Related Products

	HY57V161610DTC-10	HY57V161610DTC-15	HY57V161610D	HY57V161610DTC-6
Description	1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50	1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50	1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50	1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50
memory width	16	16	16	16
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	50	50	50	50
Maximum operating temperature	70 °C	70 °C	70 Cel	70 °C
organize	1MX16	1MX16	1M × 16	1MX16
surface mount	YES	YES	Yes	YES
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	DUAL	DUAL	pair	DUAL
Maker	SK Hynix	SK Hynix	-	SK Hynix
Parts packaging code	TSOP2	TSOP2	-	TSOP2
package instruction	TSOP2, TSOP50,.46,32	TSOP2,	-	TSOP2, TSOP50,.46,32
Contacts	50	50	-	50
Reach Compliance Code	unknow	unknow	-	unknow
ECCN code	EAR99	EAR99	-	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	-	DUAL BANK PAGE BURST
Maximum access time	7 ns	7 ns	-	5.5 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G50	R-PDSO-G50	-	R-PDSO-G50
length	20.968 mm	20.968 mm	-	20.968 mm
memory density	16777216 bi	16777216 bi	-	16777216 bi
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	-	SYNCHRONOUS DRAM
word count	1048576 words	1048576 words	-	1048576 words
character code	1000000	1000000	-	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	-	TSOP2
Package shape	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	-	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	-	1.2 mm
self refresh	YES	YES	-	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	-	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	-	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	-	3.3 V
technology	CMOS	CMOS	-	CMOS
Terminal pitch	0.8 mm	0.8 mm	-	0.8 mm
width	10.16 mm	10.16 mm	-	10.16 mm

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