February 2008
ARINC 429
Receiver with SPI Interface
PIN CONFIGURATIONS
(Top View)
44 -
43 RINA
42 RINA-40
41 -
40 VDD
39 -
38 -
37 -
36 -
35 -
34 -
- 1
RINB-40 2
RINB 3
- 4
- 5
- 6
MR 7
SI 8
CS 9
- 10
- 11
HI-3588A
GENERAL DESCRIPTION
The HI-3588A from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a Serial Peripheral Interface
(SPI) enabled microcontroller to an ARINC 429 serial bus.
The device provides one receiver with user-programmable
label recognition for any combination of 256 possible
labels, a 32 by 32 Receive FIFO and an analog line
receiver. Receive FIFO status can be monitored using the
programmable external interrupt pin, or by polling the
HI-3588A Status Register. Other features include the
ability to switch the bit-signifiance of ARINC 429 labels.
The ARINC input pins are available with different input
resistance values to provide flexibility when adding
external lightning protection circuitry.
HI-3588APCI
HI-3588APCT
IN
AR
Y
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
CS - 9
N/C - 10
N/C - 11
33 -
32 -
31 -
30 GND
29 -
28 -
27 -
26 -
25 RFLAG
24 -
23 -
The Serial Peripheral Interface minimizes the number of
host interface signals allowing for a small footprint device
which can be interfaced to a wide variety of industry-
standard microcontrollers supporting SPI. Alternatively,
the SPI signals may be controlled using just four general
purpose I/O port pins from a microcontroller or custom
FPGA. The SPI and all control signals are CMOS and TTL
compatible and support 3.3V or 5V operation.
The HI-3588A checks received data against ARINC 429
electrical, timing and protocol requirements. ARINC 429
databus timing comes from a 1 MHz clock input,
or an internal counter can derive it from higher clock
frequencies having certain fixed values, possibly the
external host processor clock.
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
M
EL
I
44
43
42
41
40
39
38
37
36
35
34
- N/C
- RINA
- RINA-40
- N/C
- VDD
- N/C
- N/C
- N/C
- N/C
- N/C
- N/C
-
-
-
SCK
-
GND
-
ACLK
SO
-
-
12
13
14
15
16
17
18
19
20
21
22
FEATURES
·
·
·
·
·
·
·
·
·
·
·
ARINC specification 429 compliant
3.3V or 5.0V logic supply operation
On-chip analog line receiver connects directly to
ARINC 429 bus
Programmable label recognition for 256 labels
32 x 32 Receive Data FIFO
Programmable data rate selection
High-speed, four-wire Serial Peripheral Interface
Label bit-order control
Parity checking may be disabled to allow 32-bit data
reception
Low power
Industrial & extended temperature ranges
PR
HI-3588APQI
HI-3588APQT
33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - N/C
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
44 - Pin Plastic Quad Flat Pack (PQFP)
(DS3588A Prelim Rev. E)
HOLT INTEGRATED CIRCUITS
www.holtic.com
N/C - 12
N/C - 13
N/C - 14
SCK - 15
N/C - 16
GND - 17
N/C - 18
ACLK - 19
SO - 20
N/C - 21
N/C - 22
02/08
HI-3588A
BLOCK DIAGRAM
VDD
ACLK
ARINC
Clock
Divider
SCK
CS
SI
SO
Control Register
Status Register
Label
Filter
Bit Map
Memory
SPI
Interface
RINA-40
RINB-40
RINA
RINB
40 Kohm
40 Kohm
ARINC 429
Line Receiver
ARINC 429
Valid word
Checker
Label
Filter
ARINC 429
Received
Data FIFO
RFLAG
GND
PIN DESCRIPTIONS
SIGNAL FUNCTION
RINB
RINB-40
MR
SI
CS
SCK
GND
ACLK
SO
RFLAG
VDD
RINA-40
RINA
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
POWER
INPUT
OUTPUT
OUTPUT
POWER
INPUT
INPUT
DESCRIPTION
ARINC receiver negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver negative input. Requires external 40K ohm resistor
Master Reset. A positive pulse clears the Receiver data FIFO and flags
SPI interface serial data input
Chip select. Data is shifted into SI and out of SO when CS is low.
SPI Clock. Data is shifted into or out of the SPI interface using SCK
Chip 0V supply. Note BOTH GND pins MUST be connected
Master timing source for the ARINC 429 receiver
SPI interface serial data output
Goes high when ARINC 429 receiver FIFO is empty (CR15=0), or full (CR15=1)
3.3V or 5.0V logic power
Alternate ARINC receiver positive input. Requires external 40K ohm resistor
ARINC receiver positive input. Direct connection to ARINC 429 bus
PULL UP / DOWN
10K ohm pull-down
10K ohm pull-down
10K ohm pull-up
10K ohm pull-down
10K ohm pull-down
HOLT INTEGRATED CIRCUITS
2
HI-3588A
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI-
3588A. When CS goes low, the next 8 clocks at the SCK pin shift
an instruction op code into the decoder, starting with the first
positive edge. The op code is fed into the SI pin, most significant bit
first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 16-bit writes to Control Register,
32-bit ARINC word writes to transmit FIFO or 256-bit writes to the
label-matching enable/disable table.
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As in write instructions,
data field bit-length varies with read instruction type.
Table 1 lists all instructions. Instructions that perform a reset or set
are executed after the last SI bit is received while CS is still low.
TABLE 1. DEFINED INSTRUCTION OP CODES
OP CODE
Hex
DATA FIELD
DESCRIPTION
00
01
02
03
04
05
06
None
None
None
None
None
None
256 bits
No instruction implemented
After the 8th op-code bit is received, perform Master Reset (MR)
After the 8th op-code bit is received, reset all label selections
After the 8th op-code bit is received, set all the label selections
Reserved
Reserved
Starting with label FF hex, consecutively set or reset each label in descending order
For example, a Data Field pattern starting with 1011 will set labels FF, FD, and
FC hex and reset label FE hex.
Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control
Register bit CR1 is set, the ARINC receiver operates from the divided ACLK clock. Allowable
values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in
no clock. Note: ACLK input frequency and division ratio must result in 1 MHz clock.
Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros
Dump the Receive FIFO. No framing. If CS held low after last word, the data will
be zeros.
Read the Status Register
Read the Control Register
Read the ACLK divide value programmed previously using op code 07 hex
Read the Label look-up memory table consecutively starting with address FF hex
No instruction implemented
No instruction implemented
Write the Control Register
07
8 bits
08
09
0A
0B
0C
0D
0E
0F
10
32 bits
variable
8 bits
16 bits
8 bits
256 bits
None
None
16 bits
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HI-3588A
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3588A contains a 16-bit Control Register which is used to
configure the device. Control Register bits CR15 - CR0 are loaded
from a 16-bit data value appended to SPI instruction 10 hex. The
Control Register contents may be read using SPI instruction
0B hex. Each bit of the Control Register has the following function:
STATUS REGISTER
The HI-3588A contains an 8-bit Status Register which can be
interrogated to determine status of the ARINC Receive FIFO. The
Status Register is read using SPI instruction 0A hex. Unused bits
are undefined and may be read as either “1” or “0”. The following
table defines the Status Register bits.
CR
Bit FUNCTION STATE
CR0
Receiver
Data Rate
Select
0
1
0
1
CR2 Enable Label
Recognition
CR3
CR4
-
Receiver
Parity Check
Enable
Receiver
Enable
0
1
X
0
1
0
1
CR6
Receiver
Decoder
-
-
-
-
0
1
CR7
CR8
CR9
CR10
-
-
X
X
0
1
CR12
CR13
CR14
CR15
-
-
-
RFLAG
Definition
X
X
X
0
1
DESCRIPTION
Data rate = CLK/10 (ARINC 429 High-Speed)
Data rate = CLK/80 (ARINC 429 Low-Speed)
ARINC CLK = ACLK input frequency
SR
Bit
SR0
FUNCTION
Receive FIFO
Empty
STATE
0
DESCRIPTION
Receiver FIFO contains valid data
Sets to One when all data has
been read. RFLAG pin reflects the
state of this bit when CR15=”0”
Receiver FIFO is empty
Receiver FIFO holds less than 16
words
Receiver FIFO holds at least 16
words
Receiver FIFO not full. RFLAG pin
reflects the state of this bit when
CR15=”1”
Receiver FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period
Undefined
Undefined
Undefined
Always “0”
Always “0”
CR1 ARINC Clock
Source Select
1
ARINC CLK = ACLK divided by the value
programmed with SPI Instruction 07 hex
Label recognition disabled
1
Label recognition enabled
Not used
Receiver parity check disabled
Receiver odd parity check enabled
Disable receiver. The HI-3588 ignores
all ARINC 429 data bus traffic
SR3
Normal operation
SR4
Receiver decoder disabled
SR5
ARINC bits 10 and 9 must match CR7 and CR8
SR6
If receiver decoder is enabled,
the ARINC bit 10 must match this bit
If receiver decoder is enabled,
the ARINC bit 9 must match this bit
Not used
Not used
Label bit order reversed (SeeTable 2)
Label bit order same as received
(See Table 2)
Not used
Not used
Not used
FLAG goes high when receive FIFO is empty
RFLAG goes high when receive FIFO is full
SPI
bit
ARINC bit
CR11=”0”
1
8
2
7
3
6
4
5
5
4
6
3
7
2
SR7
Not used
Not used
0
0
Not used
X
Not used
X
Not used
X
1
SR2
Receive FIFO
Full
0
SR1
Receive FIFO
Half Full
0
CR5
ARINC 429 DATA FORMAT
Control Register bit CR11 controls how individual bits in the
received ARINC word are mapped to the HI-3588A SPI data word
bits during data read or write operations. The following table
describes this mapping:
Table 2. SPI / ARINC bit-mapping
8
1
9
9
10
10
11 - 31
11 - 31
Data
32
32
CR11 ARINC Label
Bit Order
Label (MSB)
Label (LSB)
Label
Label
Label
Label
Label
Label
ARINC bit
CR11=”1”
1
2
3
4
5
6
7
8
9
10
11 - 31
Data
32
Label (MSB)
Label (LSB)
Label
Label
Label
Label
Label
Label
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Parity
SDI
SDI
Parity
SDI
SDI
HI-3588A
FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 RECEIVER
ARINC BUS INTERFACE
Figure 1 shows the input circuit for the ARINC 429 line receiver. The
ARINC 429 specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
ister, a low bit is clocked. Only one shift register can clock a
high bit for any given sample. All three registers clock low
bits if the differential input voltage is between defined state
voltage bands.
Valid data bits require at least three consecutive One or Zero
samples (three high bits) in the upper half of the Ones or Ze-
ros sampling shift register, and at least three consecutive Null
samples (three high bits) in the lower half of the Null sampling
shift register within the data bit interval.
A word gap Null requires at least three consecutive Null sam-
ples (three high bits) in the upper half of the Null sampling
shift register and at least three consecutive Null samples
(three high bits) in the lower half of the Null sampling shift reg-
ister. This guarantees the minimum pulse width.
RINA-40
VDD
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
RINA
ONE
GND
VDD
NULL
3. To validate the receive data bit rate, each bit must follow
its preceding bit by not less than 8 samples and not more
than 12 samples. With exactly 1MHz input clock frequency,
the acceptable data bit rates are:
HIGH SPEED
DATA BIT RATE MIN
DATA BIT RATE MAX
83K BPS
125K BPS
LOW SPEED
10.4K BPS
15.6K BPS
ZERO
RINB
RINB-40
GND
FIGURE 1. ARINC RECEIVER INPUT
The HI-3588A guarantees recognition of these levels with a common
mode voltage with respect to GND less than ±30V for the worst case
condition (3.15V supply and 13V signal level). Design tolerances
guarantee detection of the above levels, so the actual acceptance
ranges are slightly larger. If the ARINC signal (including nulls) is
outside the differential voltage ranges, the HI-3585 receiver rejects
the data.
RECEIVER LOGIC OPERATION
Figure 2 is a block diagram showing receiver logic.
BIT TIMING
The ARINC 429 specification defines the following timing toler-
ances for received data:
HIGH SPEED
100K BPS ± 1%
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
LOW SPEED
12K -14.5K BPS
10 ± 5 µsec
10 ± 5 µsec
34.5 to 41.7 µsec
4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of 3
enables the next reception.
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the parity
bit. If the result is odd, a "0" appears in the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending on the state of Control
Register bits CR2, and CR6 through CR8, the received 32-bit
ARINC word is then checked for correct decoding and label match
before it is loaded into the 32 x 32 Receive FIFO. ARINC words that
do not match required 9th and 10th ARINC bit and do not have a
label match are ignored and are not loaded into the Receive FIFO.
The table below describes this operation.
CR2
ARINC word
matches
Enabled
label
X
No
Yes
X
X
Yes
No
No
Yes
CR6
ARINC word
bits 10, 9
match
CR7,8
X
X
X
No
Yes
No
Yes
No
Yes
FIFO
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
The HI-3588A accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
1. An accurate 1MHz clock source is required to validate the
receive signal timing. Less than 0.1% error is recommended.
2. The receiver uses three separate 10-bit sampling shift reg-
isters for Ones detection, Zeros detection and Null detection.
When the input signal is within the differential voltage range
for any shift register’s state (One Zero or Null) sampling
clocks a high bit into that register. When the receive signal is
outside the differential voltage range defined for any shift reg-
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
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