FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20887-1E
FLASH MEMORY
CMOS
64 M (8 M
×
8/4 M
×
16) BIT
Dual Operation
MBM29DL640E
80/90/12
s
DESCRIPTION
The MBM29DL640E is a 64 M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 Mwords
of 16 bits each. The device is offered in 48-pin TSOP (I) and 63-ball FBGA packages. This device is designed to
be programmed in system with 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase
operations. The device can also be reprogrammed in standard EPROM programmers.
The device is organized into four physical banks: Bank A, Bank B, Bank C and Bank D, which can be considered
to be four separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu’s
standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access
from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simulta-
neously taking place on the other bank.
(Continued)
s
PRODUCT LINE UP
Part No.
Ordering Part No.
V
CC
=
3.3 V
+0.3
V
−0.3
V
V
CC
=
3.0 V
+0.6
V
−0.3
V
80
80
80
30
MBM29DL640E
90
90
90
35
12
120
120
50
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s
PACKAGES
48-pin plastic TSOP (I)
Marking Side
48-pin plastic TSOP (I)
63-ball plastic FBGA
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-63P-M02)
MBM29DL640E
80/90/12
(Continued)
In the device, a new design concept called FlexBank
TM
*
1
Architecture is implemented. Using this concept the
device can execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and
Bank 2, a bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1.
(Refer to FUNCTIONAL DESCRIPTION for Simultaneous Operation.)
The standard device offers access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed
microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write
enable (WE) and output enable (OE) controls.
This device consists of pin and command set compatible with JEDEC standard E
2
PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm
TM
which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm
TM
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies
the proper cell margin.
A sector is typically erased and verified in 1.0 second (if already completely preprogrammed) .
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once a program or erase cycle has been completed,
the device internally resets to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program
Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read
mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the
Embedded Program
TM
*
2
Algorithm or Embedded Erase
TM
*
2
Algorithm, the device is automatically reset to the
read mode and have erroneous data stored in the address locations being programmed or erased. These
locations need rewriting after the Reset. Resetting the device enables the system’s microprocessor to read the
boot-up firmware from the Flash memory.
Fujitsu’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
*1: FlexBank
TM
is a trademark of Fujitsu Limited.
*2: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
2
MBM29DL640E
80/90/12
s
FEATURES
•
0.23
µm
Process Technology
•
Simultaneous Read/Write operations (Dual Bank)
•
FlexBank
TM
Bank A : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Bank B : 24 Mbit (64 KB
×
48)
Bank C : 24 Mbit (64 KB
×
48)
Bank D : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Two virtual Banks are chosen from the combination of four physical banks (Refer to Table 9, 10)
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
•
Single 3.0 V read, program, and erase
Minimized system level power requirements
•
Compatible with JEDEC-standard commands
Uses the same software commands as E
2
PROMs
•
Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix : TN
−
Normal Bend Type, TR
−
Reversed Bend Type)
63-ball FBGA (Package suffix : PBT)
• Minimum 100,000 program/erase cycles
•
High performance
80 ns maximum access time
•
Sector erase architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode
Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode
Any combination of sectors can be concurrently erased. It also supports full chip erase.
•
Hidden ROM (Hi-ROM) region
256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•
WP/ACC input pin
At V
IL
, allows protection of “outermost” 2
×
8 Kbytes on both ends of boot sectors, regardless of sector protection/
unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
•
Embedded Erase
TM
Algorithms
Automatically preprograms and erases the chip or any sector
•
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
(Continued)
3
MBM29DL640E
80/90/12
(Continued)
•
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic sleep mode
When addresses remain stable, the device automatically switches itself to low power mode.
•
Low V
CC
write inhibit
≤
2.5 V
•
Program Suspend/Resume
Suspends the program operation to allow a read in another byte
•
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
•
Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
•
Fast Programming Function by Extended Command
•
Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
•
In accordance with CFI (Common Flash Memory Interface)
4
MBM29DL640E
80/90/12
s
PIN ASSIGNMENTS
TSOP (I)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
19
A
20
WE
RESET
A
21
WP/ACC
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
Standard Pinout
(FPT-48P-M19)
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
RY/BY
WP/ACC
A
21
RESET
WE
A
20
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
Reverse Pinout
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
(FPT-48P-M20)
(Continued)
5
京公网安备 11010802033920号
EEWORLD
