DTC143ZE datasheet, PDF - EEWORLD Datasheet

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DTC143ZE: CategoryDigital transistor; File Size2MB，15 Pages; ManufacturerJCET; Websitehttp://www.cj-elec.com/; Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

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DTC143ZE Parametric

Parameter Name	Attribute value
Transistor type	NPN
Power(Pd)	150mW
Collector current (Ic)	100mA
Collector-emitter breakdown voltage (Vceo)	50V

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD

JC T

Digital Transistors (Built-in Resistors)

DTC143ZM/DTC143ZE/DTC143ZUA

DTC143ZKA /DTC143ZCA/DTC143ZSA

DIGITAL TRANSISTOR (NPN)

·Equivalent

Circuit

FEATURES



Built-in bias resistors enable the configuration of an inverter circuit

without connecting external input resistors(see equivalent circuit)



The bias resistors consist of thin-film resistors with complete isolation

to allow negative biasing of the input.They also have the advantage of

almost completely eliminating parasitic effects



Only the on/off conditions need to be set for operation, making device design easy

PIN CONNENCTIONS and MARKING

DTC143ZM

SOT-723

1. IN

2. GND

DTC143ZE

SOT-523

1. IN

2. GND

3. OUT

MARKING:E23

MARKING: E23

DTC143ZUA

SOT-323

1. IN

2. GND

3. OUT

DTC143ZKA

SOT-23-3L

1. IN

2. GND

3. OUT

MARKING: E23

DTC143ZCA

SOT-23

1. IN

2. GND

3. OUT

DTC143ZSA

TO-92S

1. GND

2. OUT

3. IN

1 2 3

MARKING: E23

www.cj-elec.com

A,Jun,2014

F,Mar,2016

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