AME, Inc.
AME8816
1.5A CMOS LDO
n
General Description
The AME8816 family of positive, linear regulators fea-
ture low quiescent current (45µA typ.) with low dropout
voltage, making them ideal for battery applications.
Output voltages are set at the factory and trimmed to
1.5% accuracy.
These rugged devices have both Thermal Shutdown,
and Current Fold-back to prevent device failure under
the "Worst" of operating conditions.
In applications requiring a low noise, regulated supply,
place a 1000pF capacitor between Bypass and Ground.
The AME8816 is stable with an output capacitance of
4.7µF or greater.
n
Functional Block Diagram
(Fixed Versions)
IN
OUT
Overcurrent
Shutdown
Thermal
Shutdown
R1
BYPASS
AMP
EN
1.242V
R2
GND
n
Features
Very Low Dropout Voltage
l
Guaranteed 1.5A Output
l
Accurate to within 1.5%
l
45µA Quiescent Current Typically
l
Over-Temperature Shutdown
l
Current Limiting
l
Short Circuit Current Fold-back
l
Noise Reduction Bypass Capacitor (Fixed
Versions)
l
Power-Saving Shutdown Mode
l
Space-Saving DDPAK-5 Package
l
6 Factory Pre-set Output Voltages
l
Low Temperature Coefficient
l
Adjustable Version
l
n
Functional Block Diagram
(Adjustable Version)
IN
OUT
Overcurrent
Shutdown
Thermal
Shutdown
R1
AMP
EN
ADJ
1.242V
R2
(external)
(external)
GND
n
Typical Application
n
Applications
l
l
l
l
l
IN
OUT
IN
BYP
GND
OUT
AME8816
Instrumentation
Portable Electronics
Wireless Devices
PC Peripherals
Battery Powered Widgets
EN
C1
5V
C2
C3
1
µF
1nF
4.7µ
F
1
AME, Inc.
AME8816
1.5A CMOS LDO
n
Absolute M aximum Ratings:
Parameter
Input Voltage
Output Current
Output Voltage
ESD Classification
Maximum
8
Unit
V
mA
V
P
D
/ (V
IN
- V
O
)
GND - 0.3 to V
IN
+ 0.3
B
Caution: Stress above the listed absolute maximum rating may cause permanent damage to the device.
n
Recommended operating Conditions:
Parameter
Ambient Temperature Range
Junction Temperature
Rating
-40 to +85
-40 to +125
Unit
o
C
C
o
n
T hermal Information
Parameter
TO-263 (DDPAK-5)
Thermal Resistance (
θ
jc
)
SO-8
Maximum
5
20**
o
Unit
C/W
TO-263 (DDPAK-5)
Internal Power Dissipation (P
D
)
(
∆
T = 100
o
C)*
SO-8
3.00
2.50
W
Maximum Junction Temperature
Maximum Lead Temperature ( 10 Sec)
* Assuming a heat sink capable of twice times (
θ
jc
)
** Estimated
150
300
o
C
C
o
4
AME, Inc.
AME8816
1.5A CMOS LDO
n
Electrical Specifications
V
IN
= V
O(nom)
+ 2V , V
EN
= V
IN
, T A = 25
o
C unles s otherwis e noted
P a ra m e te r
Input V oltage
O utput V oltage A c c urac y
S ym b ol
V
IN
V
O
V
EN
= V
EH
m in, I
O
= 1m A
I
O
= 1.5A
V
O
= V
O N O M
-2.0%
1.5V < V
O(N O M)
< = 2.0V
2.0V < V
O(N O M)
< = 2.8V
2.8V < V
O (N O M)
O utput Current
Current Lim it
S hort Circ uit Current
Q uies c ent Current
M inim un Load Current
(For A DJ Option)
G round P in Current
I
O
I
LIM
I
SC
I
Q
I
MI N
I
G N D
I
O
= 1m A to 1.5A
I
O
= 1m A
V
IN
= V
O
+ 1 to V
O
+ 2
V
O
< 2.0V
4.0 > V
O
> = 2.0V
4.0V < = V
O
Load Regulation
O ver Tem erature S hutdown
O ver Tem erature Hy s teris is
V
O
Tem perature Coeffic ient
A DJ Input B ias Current
A DJ Referenc e V oltage
RE G
LOAD
O TS
O TH
TC
I
AD J
V
R EF
f= 1k Hz
P ower S upply Rejec tion
P S RR
I
O
= 100m A
C
O
= 4.7
µ
F c eram ic
I
O
= 100m A
P ower S upply Rejec tion
P S RR
C
O
= 4.7
µ
F c eram ic
C
BY P
= 0.01
µ
F
O utput V oltage Nois e
eN
f= 10Hz to 100k Hz
I
O
= 10m A ,C
BY P
= 0
µ
F
f= 10Hz to 100k Hz
I
O
= 10m A ,C
BY P
= 0.01
µ
F
f= 10k Hz
f= 100k Hz
f= 1k Hz
f= 10k Hz
f= 100k Hz
Co= 4.7
µ
F
Co= 4.7
µ
F
2.0
0
V
IN
= 7V
V
EN
= 0V , V
IN
= 7V
V
IN
= 5V , V
O
= 0V , V
EN
= 0V
0.5
V
IN
= 5V , V
AD J
= 1.242V
1.223
I
O
= 1m A to 1.5A
-0.15
-0.1
-0.4
-1
0.2
150
30
30
1
1.242
50
20
15
75
55
30
30
µ
V rm s
µ
V rm s
V in
0.4
0.1
0.5
2
V
V
µ
A
µ
A
µ
A
dB
dB
1.261
0.02
V
O
> 1.2V
V
O
> 1.2V
V
O
< 0.4V
I
O
= 0m A
1
45
0.15
0.1
0.4
1
1500
1500
2000
750
45
70
S ee
c hart
Te st Con dition
M in
Note 1
-1.5
Typ
Max
7
1.5
1300
800
600
mA
mA
mA
µ
A
mA
µ
A
%
%
%
%
o
o
Un its
V
%
Dropout V oltage
V
D R OPOU T
mV
Line Regulation
RE G
LIN E
C
C
ppm /
o
C
µ
A
V
O utput V oltage Nois e
eN
V
EH
V
EL
30
E N Input Thres hold
E N Input B ias Current
S hutdown S upply Current
Note1.V
IN (m in)
= V
O U T
+ V
D R OPOU T
I
EH
I
EL
I
SD
Note2.V
O(nom ) :
nom inal output voltage of fix ed vers ion
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
