Why should we pay attention to the power supply noise problem? What are the factors that cause power supply noise?

In power management design, should we pay attention to the issue of power supply noise? What are the causes of power supply noise?

1. Why should we pay attention to the problem of power supply noise?

There are thousands of transistors inside the chip, which form internal gate circuits, combinational logic, registers, counters, delay lines, state machines, and other logic functions. As chips become more and more integrated, the number of internal transistors becomes larger and larger. The number of external pins of the chip is limited, and it is unrealistic to provide a separate power supply pin for each transistor. The external power supply pin of the chip provides a common power supply node to the internal transistors, so the state transition of the internal transistors will inevitably cause the transmission of power supply noise inside the chip.

The operations of each internal transistor are usually synchronized by the core clock or the on-chip peripheral clock. However, due to differences in internal delays, the state transitions of each transistor cannot be strictly synchronized. When some transistors have completed state transitions, other transistors May still be in the conversion process. Gate circuits that are at a high level inside the chip will transmit power supply noise to the input parts of other gate circuits. If the gate circuit receiving power supply noise is in the unsteady state region of level conversion at this time, the power supply noise may be amplified and generate rectangular pulse interference at the output end of the gate circuit, thereby causing logic errors in the circuit. Noise at the chip's external power supply pin propagates through the internal gate circuit and may trigger state transitions in the internal register.

In addition to affecting the working status of the chip itself, power supply noise will also affect other parts. For example, power supply noise will affect the jitter characteristics of crystal oscillators, PLLs, and DLLs, and the conversion accuracy of AD conversion circuits. Explaining these issues requires a very long length, so I will not introduce them further in this article. I will explain them in detail in subsequent articles.

Due to changes in the operating temperature of the final product and inconsistencies generated during the production process, the circuit will be very difficult to debug if it is a problem caused by the power supply system. Therefore, it is best to follow some mature design rules at the beginning of the circuit design to make the power supply The system is more robust.

2. Power system noise margin analysis

Most chips will give a normal operating voltage range, which is usually ±5%. For example: for 3.3V voltage, in order to meet the normal operation of the chip, the supply voltage is between 3.13V and 3.47V, or 3.3V±165mV. For 1.2V voltage, in order to meet the normal operation of the chip, the supply voltage is between 1.14V and 1.26V, or 1.2V±60mV. These limitations can be found in the recommended operating conditions section of the chip datasheet. There are two parts to consider in these limitations, the first is the DC output error of the voltage regulator chip, and the second is the peak amplitude of the power supply noise. The output voltage accuracy of old voltage regulator chips is usually ±2.5%, so the peak amplitude of power supply noise should not exceed ±2.5%. Of course, with the improvement of chip technology, the DC accuracy of modern voltage regulator chips is higher, which may reach less than ±1%. TI's switching power supply chip TPS54310 has an accuracy of ±1%, and the linear voltage regulator AMS1117 can reach ±0.2%. . But remember, there are conditions to achieve such accuracy, including load conditions, operating temperature and other limitations. Therefore, the value of ±2.5% is more reliable for reliable design. If you can ensure that the chip you are using can achieve higher voltage regulation accuracy when mounted on the circuit board, then you can perform a separate noise margin calculation for your design. This article focuses on the principle explanation of the power supply part design. The value of ±2.5% will be used for the power supply noise margin.

Calculating power supply noise margin is very simple, as follows:

For example, the normal operating voltage range of the chip is between 3.13V and 3.47V, and the nominal output of the voltage regulator chip is 3.3V. After being installed on the circuit board, the voltage regulator chip outputs 3.36V. Then the allowable voltage variation range is 3.47-3.36=0.11V=110mV. The output accuracy of the voltage regulator chip is ±1%, that is, ±3.363*1%=±33.6 mV. The power supply noise margin is 110-33.6=76.4 mV.

The calculation is simple, but there are four issues to pay attention to:

First, can the output voltage of the voltage stabilizing chip be accurately set at 3.3V? The parameters of peripheral components such as resistors, capacitors, and inductors are not accurate, which affects the output voltage of the voltage stabilizing chip, so the value of 3.36V is used here. You can't predict the exact output voltage until it's installed on the board.

Second, does the working environment comply with the recommended environment in the voltage regulator chip manual? Will the parameters be consistent with those in the chip manual after the device ages?

Third, what is the load situation? This also affects the output voltage of the voltage regulator chip.

Fourth, power supply noise will ultimately affect signal quality. The source of noise on the signal is not only power supply noise. Signal integrity issues such as reflection crosstalk will also superimpose noise on the signal. All noise margin cannot be allocated to the power supply system. Therefore, you must leave room for noise when designing the power supply noise margin.

Another important issue is: Different voltage levels have different requirements for power supply noise margin. If calculated based on ±2.5%, the noise margin for the 1.2V voltage level is only 30mV. This is a very harsh restriction and should be designed with caution. Analog circuits have higher power requirements. Power supply noise affects the clock system and may cause timing matching issues. Therefore, we must pay attention to the power supply noise problem.

3. There are three sources of noise in the power system:

First, the output of the regulated power supply chip itself is not constant and will have certain ripples. This is determined by the voltage stabilizing chip itself. Once the voltage stabilizing power supply chip is selected, we can only accept this part of the noise and cannot control it.

Second, the regulated power supply cannot respond in real time to rapid changes in current demand from the load. The regulated power supply chip adjusts its output current by sensing changes in its output voltage, thereby adjusting the output voltage back to the rated output value. The time required for most commonly used voltage regulators to adjust voltage is on the order of milliseconds to microseconds. Therefore, when the load current changes frequency between DC and several hundred KHz, the voltage regulator can make good adjustments to maintain the stability of the output voltage. When the load transient current change frequency exceeds this range, the voltage output of the voltage regulator will drop, resulting in power supply noise. Today, microprocessor core and peripheral clock frequencies have exceeded 600 MHz, and internal transistor level transition times have dropped to less than 800 picoseconds. This requires that the power distribution system must be able to respond quickly to changes in load current in the range from DC to 1GHz, but it is impossible for existing regulated power supply chips to meet this stringent requirement. We can only use other methods to compensate for the lack of a regulated voltage source, which involves power supply decoupling to be discussed later.

Third, the voltage drop caused by the load transient current in the power path impedance and ground path impedance. Impedance is inevitable in any electrical path on a PCB, whether it's a full power plane or a power lead. For multilayer boards, a complete power plane and ground plane are usually provided. The regulated power output is first connected to the power plane, and the supply current flows through the power plane and reaches the load power pin. The ground path is similar to the power path, except that the current path becomes the ground plane. The impedance of a full plane is low, but it's there. If you use leads instead of planes, the impedance on the path will be higher. In addition, the pins and pads themselves will also have parasitic inductance. The transient current flowing through this path will inevitably produce a voltage drop. Therefore, the voltage at the power supply pin of the load chip will fluctuate with the change of the transient current. This is the impedance. generated power supply noise.