Principles and precautions of active discharge circuit

    The multiple power rails of today's FPGAs and high-performance processors must be powered up and powered down in a strict sequence. The decoupling capacitors typically connected to the power rails must be actively discharged to ensure that the power-down sequence is properly controlled and completed within an acceptable time. This article describes the principles and design of active discharge circuits and explains the selection criteria for key components such as power MOSFETs to ensure repeatable performance and reliability.

    introduce

    Many of today’s system-on-chip FPGAs, ASICs, and application processors require multiple individual power rails to power low-voltage core logic, 3.3V or 5V I/O, and other circuits such as memory buses or 1.2V Ethernet drivers. It is well known that powering up these rails in the correct order is critical to ensuring proper system operation. Power sequencers are used to enable each point-of-load (POL) converter in turn, bringing up each rail at the correct time. Ensuring that the power-down process follows the reverse order is equally important, but decoupling capacitors on the power lines prevent the system from powering down properly. Unless these capacitors are actively discharged, the remaining charge decays at an undetermined rate after the POL is disabled, potentially disrupting the sequence.

    Active capacitor discharge

    The discharge time of each decoupling capacitor can be controlled using a series resistor to set the RC time constant. This enables the sequencer to shut down each POL after a known time delay after the previous converter in the sequence was deactivated. The resistor values ​​should be chosen to discharge the capacitor to 5% of its fully charged voltage in a suitable time, avoiding excessive discharge current and noise, but also allowing the sequence to complete in an acceptable time after the signal to shut down the system has been received.

    The schematic diagram of Figure 1 illustrates the active discharge design from Diodes Incorporated, which uses an N-channel power MOSFET DMN3027LFG (Q2) as a switch to discharge the decoupling capacitor to ground through resistor R2, which is selected to achieve a suitable RC time constant. The presence of R2 also prevents sharp current peaks that could cause EMI issues and transient thermal stress on the N-channel power MOSFET and capacitor bank.

    Figure 1. Active capacitor discharge is critical to proper power-down sequencing.

    In Figure 1, the EN output of the power sequencer is connected to the enable pin of the DC-DC regulator and also to the gate of a P-channel MOSFET (Q1). When the sequencer output goes low to disable the DC-DC regulator, Q1 inverts the signal, turning on Q2 to discharge the capacitor. The discharge circuit assumes that the DC-DC regulator cannot continue to produce output once the shutdown signal is applied. If power is available at the output of the DC-DC regulator after the shutdown command is activated, Q2 will attempt to sink the full output current capability of the DC-DC regulator. This must be prevented by inserting a delay before activating the discharge circuit.

    Key component selection

    Although the active discharge circuit is easy to implement, care needs to be taken in selecting the correct resistors and P-channel and N-channel MOSFETs to minimize the effects of transients and overheating that can degrade reliability.

    The selection of MOSFET Q1 should be made with reference to the output voltage threshold of the power sequencer. The selected device should have a high enough gate threshold voltage (VGS(th)) to ensure that it remains off when the sequencer output is high, keeping in mind that VGS(th) decreases with increasing junction temperature. The sequencer selected for this example is powered by a 5V supply and has a minimum specified high-level output voltage of 4.19V. At an ambient operating temperature of 60°C, Q1's VGS(th) must be greater than 0.9V to ensure proper operation. In addition, a 100kΩ resistor should be used to pull the gate down to the source potential to avoid false turn-on. Inspection of the normalized curve of VGS(th) versus temperature in the MOSFET datasheet shows that the ZXMP6A13F from Diodes Incorporated meets the requirements: the guaranteed minimum VGS(th) is 1V at room temperature, dropping to around 0.9V at +60°C.

    For the purposes of this example, let's assume that the sequencer must shut down a total of 10 voltage rails within 100 milliseconds. Therefore, the decoupling capacitor bank on each rail must discharge within 10 milliseconds. Targeting a 3x RC time constant of 8ms ensures that the capacitors discharge to less than 5% of their full voltage within the required time. To calculate the RC constant, the MOSFET RDS(ON), parasitic trace resistance and ESR of the capacitor bank, and resistor R2 must be considered.

    Assuming the sum of the capacitor ESR and trace resistance is no greater than 10mΩ, and the total capacitance of the decoupling group is 15mF, the appropriate values ​​of RDS(ON) and R2 can be calculated as follows:

    3 x (10mΩ + R2 + (1.5 x RDS(ON))) x 15mF = 8ms

    Assuming R2 = 50mΩ, the RDS(ON) of power MOSFET Q2 must be less than 80mΩ at VGS = 4.5V and 25°C ambient temperature.

    When selecting a MOSFET, the effects of temperature-related variations and batch-to-batch variations in RDS(ON) should also be considered. Over the expected operating temperature range for a 4.5V gate drive, RDS(ON) can vary by as much as 15mΩ. For this reason, it is best to ensure that R2 is approximately twice the maximum RDS(ON) specified by the manufacturer of the selected MOSFET. If R2 is 50mΩ, a MOSFET such as the DMN3027LFG N-channel MOSFET from Diodes Incorporated can be selected. The typical and maximum RDS(ON) of this device at VGS = 4.5V at room temperature are 22mΩ and 26.5mΩ, respectively. Therefore, RDS(ON) can vary from approximately 15mΩ to 40mΩ, providing a 95% (3x RC) discharge time between 3.9 and 5.4ms, with a worst-case capacitor bank size of 20mF.

    Assessing safe operating areas

    Because the DMN3027LFG capacitor’s energy is dissipated over time as a function of current and voltage, it is necessary to evaluate the maximum single pulse that the power MOSFET can safely handle while ensuring that the junction temperature does not exceed the absolute maximum rating, typically TJ(max) = +150°C. This can be seen by examining the safe operating area (SOA) in the MOSFET datasheet (Figure 2). The SOA should be based on the ambient operating temperature of the application and the required MOSFET gate drive. An acceptable SOA curve should show a single pulse peak current capability of at least 1V for pulse widths between 1ms and 10ms when discharging a 0.9V charged capacitor bank. The SOA should apply to the typical application ambient temperature, assumed to be +60°C, while mounted on a PCB with minimal heat sinking,

    Figure 2. SOA of the DMN3027LFG N-channel MOSFET.

    The power dissipation in the DMN3027LFG (Q2) MOSFET and series resistor R2 also needs to be considered. The worst case is caused by the capacitor charging and discharging in short periods of time. Assuming that in the worst case, the power sequencer can enter a continuous loop that enables and disables the DC-DC regulator every 20 ms (10 ms enable + 10 ms disable), the DMN3027LFG and R2 will dissipate approximately 0.5 W. This is calculated by knowing that the total energy stored in the capacitor bank will be released every 20 ms:

    P = E ÷ t = ½CV2 ÷ 20ms = 500mW (assuming C = 20mF charged to 1V)

    Since the maximum temperature-regulated RDS(ON) of the DMN3027LFG is 40mΩ, the power dissipation in Q2 and R2 is 222mW and 278mW respectively. At the minimum RDS(ON) of 15mΩ, the power dissipation in R2 increases to 385mW. Therefore, a 0.5W rated resistor is required.

    In a typical application, where the ambient temperature is expected to reach 60°C, the DMN3027LFG has a junction-to-ambient thermal resistance (RθJA) of 130°C/W on the recommended minimum pad layout, and then TJ reaches 90°C while dissipating 222mW. This provides ample headroom at TJ(max) = 150°C.

    Putting computing into practice

    For testing purposes, a capacitor bank consisting of six 2,200µF electrolytic capacitors (13.2mF nominal total) and an active discharge circuit was assembled, including a Diodes Incorporated ZXMP6A13F P-channel MOSFET (Q1) and a DMN3027LFG N-channel MOSFET (Q2) as shown in Figure 1. The ZXMP6A13F was manually triggered using a 5V signal.

    Figure 3. Results recorded without (left) and with (right) a 50mΩ series discharge resistor.

    First, the capacitor bank is discharged through the DMN3027LFG alone to illustrate the effect of adding the 50mΩ resistor R2. Figure 3 shows that the peak current reaches about 30A, but this will decrease at higher temperatures due to the increased MOSFET RDS(ON). Adding R2 limits the peak current to about 11A, while also reducing the temperature dependence of the discharge current. With the resistors in the circuit, the time to discharge to 95% of the initial 1V charge state is 3 to 4ms, close to the theoretically calculated figure.

    in conclusion

    When working with complex FPGA and system-on-chip devices that run from multiple power rails, shutting down each POL in the correct order is just as important as ensuring the correct power-up sequence. This is necessary to prevent damage to parts of the chip. However, when powered down, decoupling capacitors that are essential when the system is operating normally can cause the shutdown time to become unpredictable. Actively discharging these capacitors to ensure that each power rail is shut down in a known time allows for a correct and safe shutdown.

    Taking the time to consider worst-case scenarios and stress on components such as power MOSFET switches can pay off by ensuring long-term reliability and minimizing reliance on environmental influences such as temperature.