Positive and negative peak detection circuit with hold control composed of SMP04 and op amp

As shown in the figure, it is a positive and negative peak detection circuit with hold control composed of SMP04 and op amp. Amplifier A is used for positive peak detection, and amplifier B is used for negative peak detection. Assuming that the internal sample-and-hold switch of SMP04 is closed, when the positive input voltage VIN rises, the output of the positive peak detection amplifier A turns on D2 and turns off D1, the feedback loop of amplifier A is disconnected, and the sample-and-hold amplifier SMP04 outputs "VOUT positive" to track input changes. On the contrary, the output of the negative peak detection amplifier B turns off D4 and turns on D3, and the sample-and-hold amplifier SMP04 outputs "VOUT negative" to hold the last maximum input negative peak voltage. When the positive input voltage VIN drops from the maximum value and is lower than the voltage on the holding capacitor, D2 turns off and D1 turns on, and the sample-and-hold amplifier SMP04 outputs "VOUT positive" to hold the maximum value (peak value) of the positive input voltage VIN on the holding capacitor before; similarly, the output of the negative peak detection amplifier B turns on D4 and turns off D3, and the sample-and-hold amplifier SMP04 outputs "VOUT negative" to start tracking input changes. In this way, the positive and negative peak voltages are detected and output from the "VOUT positive" and "VOUT negative" terminals respectively. In the peak hold stage, the PD non-/H control signal is high, and the internal sampling and holding switch of SMP04 is disconnected, which can reduce the leakage current of the holding capacitor. When the "reset" signal is high, Q1 and Q2 are turned on, clamping the input terminal of SMP04 to zero, that is, reset occurs.