Interface address decoding circuit

The working principle of this interface is as follows: First, the PC performs a write operation on the encrypted I/O port through the interface address decoding circuit
(see circle 27-5). At this time, csl is low level (valid). IOW is low level (valid), if PCAO is also 0. Then start the AD574's 12-bit precision
A/D conversion ; if PCAO is 1. Then start A/D conversion with 8-bit precision. After the AD574 is started, it needs to wait for 25ys before the A/D conversion can be completed . For the A/D interface in timing mode, after the computer starts the A/D conversion and the delay is greater than 25ps, the V D conversion result
can be read out from the AD574.
;For the A/D interface in query mode. The PC makes cso valid (low level) through the interface address code circuit, outputs
the A/D conversion result of AD574 as a signal, and sends it to the data bus of the computer through 74LS125 and 74LS245. The computer determines
the status . If If the child bit is 1, A/D conversion is still in progress; if the bit is 0, the A/D conversion is completed. At this time, PC can make CS1 valid (low level)
and IOW without E (high level). For AD574 reading data, when PCAO is low level, the high 8-bit data of the A/D conversion result is read; when PQAO is high level
, the low 4-bit data and 4 zeros of the A/D conversion result are read.