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Integrated counter function analysis and application

Source: InternetPublisher:武林萌主 Updated: 2019/01/05

Relevant key device information applied in this article: T210 There are many varieties of integrated counters today, which can be divided into two categories according to their functions: synchronous and asynchronous. This section introduces two integrated counters: asynchronous integrated counter T210 and synchronous integrated counter T214. When studying, you should pay attention to the counting functions and uses of these two counters and use the integrated counter as the core component of the circuit to design the logic circuit. 1. Asynchronous integrated counter T210 T210 asynchronous 2-5-10 base counter is composed of four JK It is composed of a flip-flop and two NAND gates. Its logic symbol is: As shown in Figure (1), its logic function is described as follows: (Function table as shown in Figure (2)) Clear "0" function (output is "0000"): When the inputs of R0(1) and R0(2) are all high level and S9(1) and S9(2) are low level, the output of each flip-flop is "0", realizing clearing "0" "function, because the clock is not synchronized, this clearing is also called "asynchronous clearing". Set "9" function (output is "1001"): When S9(1), S9(2) inputs are both high level , when R0(1) and R0(2) have low level, the trigger output is "1001", realizing the "9" function; Counting function: when R0(1), R0(2) and S9(1), S9 (2) When there is a low level, each flip-flop returns to its normal function and realizes the counting function. When using it, you must follow the requirements of the function table. Example 1. Use T210 to form a nine-digit counter. If you choose 8421BCD decimal counter, and the initial state is "0", then select "0--8" as the valid state. When the counting pulse is "9", the output is QDQCQBQA="1001 ", immediately changes it to "0000", causing the counter to return to the initial state. Its logic circuit diagram is: As shown in Figure (3), this function uses the feedback method to reset the counter to "0", so that The large modulus counter is changed to a small modulus counter. Since T210 clears "0" asynchronously, a transition state is required. If a counter with a larger modulus is needed, the modulus can be increased through cascading. For example: the two-level T210 can be expanded to a 2--99 hexadecimal counter when connected. 2. Synchronous integrated counter T214 T214 synchronous two---hexadecimal counter is composed of a four-level JK flip-flop and some control gates. Its The logic symbol is: (As shown in Figure (1)) Its logical function can be described as follows: (Function table as shown in Figure 2) Asynchronous clearing: When the clearing control terminal Cr=0, it is cleared immediately, and CP pulse has nothing to do; Synchronous preset: When the preset terminal LD=0, Cr=1, a certain data is preset at the preset input terminals A, B, C, and D. At the rising edge of CP, the data of ABCD is sent to Enter the counter; (must be used synchronously with the pulse) Hold: When LD=Cr=1, when there is a low level in the control terminals P and T, the J=K=0 of each stage of the flip-flop is in the hold state; Counting: When LD=Cr=T=P=1, the circuit is a modulo 24 synchronous up counter. When the output is "1111", the carry output terminal Oc sends a high-level carry signal, that is, Oc=QAQBQCQD*T=1. Note: Since T214 has a preset end, you can use this function to form an arbitrary counter. It can also use the feedback method to form a counter like T210. Example 1. Use the synchronous preset end of T214 to form an octal counter. If the first eight states are selected. , then the subsequent state is invalid. When the counter output is "0111", it is fed back to the synchronous preset terminal through the "NAND" gate, so that LD=0, and another clock pulse comes, and the counter is preset to "0" again. The circuit diagram is: As shown in Figure (3), if the middle eight states are selected: starting from "0011", when the counter output is "1010", it is fed back to the synchronous preset terminal through the "NAND" gate to make LD=0. There is another clock pulse, and the counter is preset to "0". Its circuit diagram is: As shown in Figure (4), if you want to form a counter with a larger modulus, you can also use cascading, but you should pay attention to the connection method of Oc. .

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