Clock switching circuit and its precautions

Now that we have finished talking about the clock synchronization issue, let’s start with another common situation in SOC. Sometimes, in order to consider power consumption and performance issues, a certain module may work at one frequency in one case and another in another case. If you want to work at another frequency, you need to switch the mux at this time. Some people will say, it's not that simple, just add a mux, but is this really the case?

As shown in the picture above, everyone will naturally think of a clock switching circuit. However, if you analyze it carefully, you will find that the circuit will have the following problems, glitches! This glitch is not a good thing for either clk0 or clk1, and it does not belong to any For a clock domain, its pulse width cannot be determined at all. The point you switch will affect the width of the glitch.

So how to eliminate burrs and eliminate possible problems later? See the figure below and add a feedback circuit.

The feedback is to ensure that the clock is really turned off. For example, select switches from 0 to 1, that is, selects clk1, but at this time, make sure that clk0 is completely turned off, so the 1 is fed back through the DFF of the clk0 clock domain (if it can be fed back 1 indicates that 0 has entered the DFF of the clk0 clock domain) and is ANDed with the select of the clk1 clock domain.

In addition, in order to solve the cross-clock domain problem (select is different from the clk0 and clk1 clock domains after all), 1-2 levels of DFF are usually added.

In addition, one thing to note when using these circuits is that both clks must oscillate before selecting can be performed. Otherwise, switching may cause the select to not be correctly transmitted to the last level AND gate, thus eliminating glitches. function may not work.