Digital circuit sound and light control stair delay switch circuit (3)

It is a sound and light controlled stairway delay lighting switch with a relatively simple circuit, but has reliable performance. It
also uses a two-wire system with the power supply and light bulb. It can directly replace the ordinary lighting switch, and the original lighting circuit must be changed.
    NAND gate I_}a serves as a microphone audio amplifier, LNOR gate II constitutes a light control circuit, and NAND gate III constitutes a thyristor
delay switch. During the day, the photoresistor RI. It shows low resistance, NAND gate II outputs high level, and VD1 is cut off,
so the circuit blocks the sound channel and prevents sound pulses from passing through, so the lb light E cannot light up, which is RI at night. The dry
island resistor makes one input terminal of E-NOT gate II be logic high}U level "l", which creates
conditions for the opening of the sound channel. If someone is walking or talking on the stairs at this time, microphone B picks up the sound signal and adds it to R through non-rli amplification
output via G coupling. Both ends of , that is, the other input end of NAND fjⅡ. When
the half-cycle peak level of the frequency signal exceeds the input threshold level of NAND, both input terminals of NAND and NAND are logic
"1", and the output terminal is logic "1". ", VD1 is turned on so that the input terminal of NAND gate III is logic". ", the output
terminal is logic "l". This high level is added to the gate of the thyristor wr through R, causing VT to trigger and turn on, and the lamp E
lights up. At the same time, the moment VD1 is turned on, (. is quickly charged. In the sound After the signal, although VD1 returned to
cut-off, due to C. The stored charge needs to be slowly discharged through the high-value resistor R, so that the input terminal of NAND gate III
still maintains a low level ".", so the light E will not go out immediately. . As C. discharges,
the input level of NAND gate III continues to be high. When it rises to the NAND gate threshold level, NAND gate III flips, and the input H1 end becomes
low level . " , the crystal j Wei tube VT is turned off when the alternating current crosses zero, and the lamp F 4 goes out. The delay time of the circuit is mainly determined by the discharge time constant of R, f, and the value of R can be adjusted by
    increasing or decreasing R. Or (1:
The delay time of the circuit. In the figure, the NAND gate I-Ⅲ adopts the 2-input terminal four NAND gate
digital integrated circuit CD4011. Another NAND gate in the integrated block should have two input terminals. Grounding
treatment (that is, connected to the 7th pin). Do not leave them floating to prevent them from being affected by the interference level.