Analysis of the circuit diagram of the hierarchical priority encoder

Figure 1 shows a hierarchical priority encoder circuit. According to Wikipedia, a priority encoder is an electronic circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is a binary representation of an ordinal number starting with zero for the most significant input bit. They are often used to control interrupt requests by processing the highest priority request.

The exception priority encoder encodes only the highest order data line. But in many cases, not only the highest priority information is needed , but also the second highest priority information. The circuit presented here encodes the highest priority information and the second highest priority information of 8 lines of input data. The circuit uses the standard octal priority encoder 74148, which is an 8-line to 3-line (4-2-1) binary encoder with "low" valid data inputs and outputs.

The first encoder ( IC 1) generates the highest priority value, for example, F. The active "low" outputs of IC1 (A0, A1, A2) are inverted by gates N9 to N11 and fed to a 3-line to 8-line decoder (74138), which requires an active "high" input. The decoded outputs are active "low". The decoder identifies the highest priority data line and negates that data value using XNOR gates (N1 to N8) to retain the second highest priority value generated by the second encoder.

To understand the logic, let the input data lines be denoted L0 to L7. Lp is the highest priority line (active - "low") and Lq is the next highest priority line (active - "low"). Therefore Lp = 0 and Lq = 0. All lines above Lp and between Lp and Lq (denoted Lj) are at logic 1. All lines below the Lq logic state are irrelevant, or "don't care". Here p is the highest priority value and q is the next highest priority value. (Obviously, q must be less than p, and the smallest possible value of p is considered "1".)

Priority encoder IC1 generates binary outputs F2, F1, F0 which represent the value of p in "active low" format. The complemented F2, F1 and F0 are applied to the 3-line to 8-line (one of the eight outputs is "active low") decoder 74138. Let the output lines of 74138 be denoted as M0 to M7. Now only one line among M0 to M7 is "active low", that is Mp (where the value of p is as mentioned above). Therefore the logic level of Mp line is "0" and the logic level of the other M lines is "1".

As shown in the figure, the highest priority line is cancelled using eight XNOR gates. Let the output lines of the XNOR gates be N0 to N7. Consider the inputs Lp and Mp of the corresponding XNOR gates. Since Mp=0 and Lp=0, the output of this XNOR gate is the complement of Np=Lp=1. All other L's will not change because the corresponding M's are all 1's. Therefore, data lines N0 to N7 are the same as L0 to L7, except that the highest priority in L0 to L7 is cancelled in N0 to N7.

The highest priority among N0 to N7 is the second highest priority remaining from L0 to L7, that is, Nq=0 and Nj=1 for q to priority encoder 2 (IC3) to generate S2, S1, S0 representing q. Thus, the second highest priority value is extracted. The third highest priority can be recovered by cascading, and so on.

For example, let L0 to L7 = XXX01101. Here the highest "0" row is L6, and the next highest row is L3 (X means "don't care"). So p = 6 and q = 3. Now the "low" valid output of the first priority encoder will be F2F1F0 = 001. The input to the 74138 is 110, and it outputs M0 to M7 = 11111101. Since M6 = 0, only L6 is complemented by the XNOR gate.

Therefore, the output of XNOR is N0 to N7 = XXX01111. Now N3 = 0, and the highest priority of "N" is 3. Priority encoder 2 (IC3) restores this value to S2S1S0 = 100.