FPGA Basic Learning - D Flip-Flops, Waveforms, Code

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FPGA Basic Learning - D Flip-Flops, Waveforms, Code [Copy link]

Before learning Verilog, let's learn about the D flip-flop and its code.

The design basis of FPGA is digital circuit, so many students think that we should learn digital circuit first before learning FPGA. However, there are many contents in digital circuit textbooks. For example: JK flip-flop, RS flip-flop, truth table, Karnaugh map, etc. However, many of the contents here are actually outdated. In addition, for the study of FPGA, we only use a very small part of it. If you don't have the foundation of digital circuits, we suggest you just read part of it and know that D flip-flop is enough.

So what does a D flip-flop look like?

This is the schematic diagram of a D flip-flop. Among them, clk is the clock, rst_n is the reset, d is the input, and q is the output. This function is very simple. When the reset is valid, you can think of the value of q as 0. If the reset is invalid, then at the rising edge of the clock, the value of d is given to q. It is that simple. Remember this action. First there is a rising edge of the clock, and then the value of d is given to q. This means that the value of q remains unchanged when the clock rises. Only after the rising edge of the clock does the value of q change. This is a very important concept, that is, the rising edge of the clock must come first before the change of q. If the next rising edge of the clock does not come, the value of q remains unchanged. Therefore, the value of q changes a little bit after the rising edge of the clock. This is the D flip-flop, and all our FPGA circuits are designed based on this structure. It is that simple. JK flip-flops, RS flip-flops, etc. are not needed at all. We use the simplest result for design. Some students may ask why it is so simple to design? In fact, if we want to make a system, a stable system, it must be built from the simplest structure, not a very complex structure. Therefore, our FPGA circuit uses the stability of the D flip-flop to build it.

So what is the waveform diagram corresponding to the D flip-flop?

This is the waveform diagram. You can take a look at q. It changes after the rising edge of the clock. At the rising edge of the second clock, the value of d is 0, so q outputs 0, and the value of q remains unchanged until the next rising edge of the clock. At the next rising edge of the clock, the value of d is 1, so q outputs 1, and so on. This is the function of our D flip-flop, very, very simple.

So how do we describe this D flip-flop in FPGA using Verilog code?

In fact, this is the code. You can see that this code is exactly the same as this D flip-flop, and it describes the D flip-flop. How to explain, you can analyze this code:

1····Always (always) execute code 2~8 when the clock (clk) rises (posedge) or falls (negedge) resets (rst_n). If not satisfied, the value of q remains unchanged.

2····If it is a reset, execute code 3;

3····q is equal to 0;

[ color=#000000]5····If it is not reset, but the rising edge of the clock, execute the code of 6;

6····Give the value of d to q;

This code describes a D flip-flop, and an always generates a D flip-flop. You can think of the D flip-flop as a component in our circuit.

Summary points:

1. The value of q only changes on the rising edge of the clock.

2.When the clock rises, the value of d is assigned to q. That is, the rising edge comes first, and then the signal changes. Why is it emphasized that the rising edge comes first, and then the signal changes? What is the use? For example: The waveform of Mingdeyang is a synchronous signal by default, which means that both en and dout are generated by D flip-flops. Therefore, the signal changes only start after the rising edge of the clock, and en also changes a little bit after the rising edge of the clock; at the rising edge of 2, the value of en is 0, because en has not changed; at the rising edge of 3, the value of en is 1 and the value of dout is 0; finally, at the rising edge of 10, the value of dout is 1.