Power Circuit Breaker to Prevent ESD-Induced Device Latchup

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Power Circuit Breaker to Prevent ESD-Induced Device Latchup [Copy link]

By Emerson Segura

In some cases, ESD (electrostatic discharge) events can damage digital circuits and cause latch-up. For example, a parasitic transistor that is usually part of a CMOS device can behave as an SCR (silicon controlled rectifier) when triggered by ESD. Once the ESD is triggered, the SCR forms a low resistance channel between the two parts of the CMOS device and conducts a lot of electricity. Unless the power to the circuit is immediately removed, the device will be damaged. ESD generated by human interaction is a big problem encountered in mobile phones and medical devices. In order to have adequate ESD protection, most medical and industrial equipment requires a ground loop for ESD current. In real life, mobile devices can cope with the use of environments without a proper power ground lead.
　　To prevent expensive equipment from latch-up failures even without ESD grounding, a power disconnect circuit as shown in the figure can be added to prevent damage caused by ESD-induced latch-up. Under normal circumstances, the current drawn by the device susceptible to ESD will produce a small voltage drop across resistor R6. The voltage divider formed by R4 and R5 defines a reset current threshold for the LED port of optoisolator IC1, where the LED is off under normal operating current consumption. The _output
of 　　IC1 controls the gate bias applied to MOSFET Q1, _{which is} normally on. When latch-up occurs, the supply current can quickly increase by one or more orders of magnitude. The high voltage drop across _{R6 forward biases IC1} 's LED, so IC1 _'s phototransistor turns on, turning off Q1 _and interrupting the DC power supply to the ESD-affected device for several milliseconds. In addition, the system's firmware must be designed to allow automatic recovery from power interruptions.

　　The following equation describes the relationship between the reset current threshold and the values of R4 and R5: (R4 ₊ R5 ₎ /R4 ₌ ( _IT ×R6 ₎ /VLED _, where:IT≥ ₍ VLED ₎ / _R6 , and VCC _> VLED _. The
　　fault threshold current IT caused by ESD is greater than or equal to the forward voltage drop of the opto-isolator LED divided by the value of the sense resistor R6 _. In addition, the original supply voltage must be greater than the forward voltage drop of the LED. Resistor R1 _provides a path for IC1 _{'s base leakage current, and resistors R3} and R2 _determine the gate turn-off bias of Q1. _In
　　Figure 1, the opto-isolator LED forward voltage drop is 1.2V. For the component values shown in the figure, the circuit briefly interrupts VCC when the supply current caused by ESD exceeds about 300mA.

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