Design and Optimization of Logic Built-in Self-Test Phase Shifter*

JasonYoo

Design and Optimization of Logic Built-in Self-Test Phase Shifter* [Copy link]

The logic built-in self-test (Logic BIST) test structure is the development direction of chip testing in the future system-on-chip (SOC) design. Due to the high correlation of the pseudo-random sequence generated by the LFSR (Linear Feedback Shift Register), the fault coverage rate cannot meet the requirements. The use of phase shifters can reduce the spatial correlation of random sequences and improve the fault coverage rate of Logic BIST. This paper analyzes the mathematical theory of phase shifters and proposes a phase shifter design and optimization algorithm. The algorithm can obtain an efficient phase shifter with minimum delay and area cost.

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Phase shifters can reduce the spatial correlation of random sequences and improve the fault coverage of Logic BIST.

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