【Digital Circuit】Basic logic gate discrete component circuit

1. Project Introduction
  Logic gate is the basic unit in digital circuit, which can realize various logical relationships. The basic logic gate discrete component circuit is built with MOS tube to realize the verification of logical operations such as AND, OR, NOT, NAND, NOR, XOR and XOR.
2. Principle Analysis
1.1 PMOS
      PMOS refers to a MOS tube with N-type substrate (SUB), P channel, and current transported by the flow of holes. Negative charge attraction is required to form a conduction channel, low level conduction, and high level cutoff.
Figure 1-1-1 PMOS symbol and structural diagram
  When using PMOS control, it is usually used as an upper tube and placed above the load. A pull-up resistor is often added to the PMOS to keep the PMOS gate in a stable high level initial state, prevent the PMOS gate level from being disturbed by the outside world and produce an uncertain state, and ensure that the PMOS is in the off state by default. When P0 gives a low level, the PMOS turns on and the LED lights up; when P0 gives a high level, the PMOS turns off and the LED goes out.
Figure 1-1-2 PMOS switch control circuit Figure
1.2 NMOS
      NMOS refers to a MOS tube with a P-type substrate (SUB) and an N-channel, which transports current by the flow of electrons. The formation of a conduction channel requires positive charge attraction, high level conduction, and low level cutoff.
Figure 1-2-1 NMOS symbol and structural diagram
  When using NMOS control, it is usually used as a lower tube and placed under the load. A pull-down resistor is often added to the NMOS to keep the NMOS gate in a stable low-level initial state to prevent the NMOS gate level from being disturbed by the outside world and generating an uncertain state, ensuring that the NMOS is in the off state by default. When N0 gives a low level, the NMOS is turned off and the LED goes out; when N0 gives a high level, the NMOS is turned on and the LED lights up.
Figure 1-2-2 NMOS switch control circuit Figure
1.3 CMOS
      CMOS is composed of PMOS and NMOS in a symmetrical and complementary form, and C stands for "complementary". It has low static power consumption, fast switching speed, strong anti-interference ability, high working efficiency, high integration, and excellent performance.
2.1 AND gate
  AND gate, also known as logical product circuit. The output is high (logic 1) only when both inputs are high (logic 1), otherwise the output is low (logic 0).
 
Figure 2-1-1 AND gate logic symbol (rectangular national standard symbol and shape characteristic symbol)
 
Table 1-1 AND gate truth table

Input


Output


A1


B1


Y1


0


0


0


0


1


0


1


0


0


1


1


1Logical

expression: Y1=A1·B1
Figure 2-1-2 The
working principle of CMOS AND gate circuit is:
① When A1 inputs low level and B1 inputs low level, Q1, Q2, Q5 are turned on, Q3, Q4, Q6 are turned off, and Y1 outputs low level;
② When A1 inputs low level and B1 inputs high level, Q2, Q5, Q6 are turned on, Q1, Q3, Q4 are turned off, and Y1 outputs low level;
③ When A1 inputs high level and B1 inputs low level, Q1, Q4, Q5 are turned on, Q2, Q3, Q6 are turned off, and Y1 outputs low level;
④ When A1 inputs high level and B1 inputs high level, Q3, Q4, Q6 are turned on, Q1, Q2, Q5 are turned off, and Y1 outputs high level;
Figure 2-1-3 CMOS AND gate circuit working principle diagram Figure
2.2 OR gate
  OR gate, also known as logic and circuit. As long as one of the inputs is high level (logic 1), the output is high level (logic 1); only when the inputs are low level (logic 0), the output is low level (logic 0).
 
Figure 2-2-1 OR gate logic symbol (rectangular national standard symbol and shape characteristic symbol)
 
Table 1-2 OR gate truth table

Input


Output


A2


B2


Y2


0


0


0


0


1


1


1


0


1


1


1


1

Logical expression: Y2=A2+B2
Figure 2-2-2 The working principle of CMOS OR gate circuit
is:
① When A2 inputs low level and B2 inputs low level, Q1, Q2, Q6 are turned on, Q3, Q4, Q5 are turned off, and Y2 outputs low level;
② When A2 inputs low level and B2 inputs high level, Q1, Q3, Q5 are turned on, Q2, Q4, Q6 are turned off, and Y2 outputs high level; ③ When
A2 inputs high level and B2 inputs low level, Q2, Q3, Q4 are turned on, Q1, Q5, Q6 are turned off, and Y2 outputs high level;
④ When A2 inputs high level and B2 inputs high level, Q3, Q4, Q5 are turned on, Q1, Q2, Q6 are turned off, and Y2 outputs high level;
Figure 2-2-3 CMOS OR gate working principle Figure
2.3 NOT gate
  NOT gate, also known as logic negation circuit. When the input is low level (logic 0), the output is high level (logic 1); when the input is high level (logic 1), the output is low level (logic 0).
 
Figure 2-3-1 NOT gate logic symbol (rectangular national standard symbol and shape characteristic symbol)
 
Table 1-3 NOT gate truth table


Input


Output


A3


Y3


0


1


1


0


Logical expression: Y3=A3'
Figure 2-3-2 The working principle of CMOS NOT gate circuit
is:
① When A3 inputs a low level, Q1 is turned on, Q2 is turned off, and Y3 outputs a high level;
② When A3 inputs a high level, Q2 is turned on, Q1 is turned off, and Y3 outputs a low level;
Figure 2-3-3 CMOS NOT gate circuit working principle Figure
2.4 NAND gate
  The NAND gate is a combination of an AND gate and a NOT gate. The output is low (logic 0) only when both inputs are high (logic 1), otherwise the output is high (logic 1).
 
Figure 2-4-1 NAND gate logic symbol (rectangular national standard symbol and shape characteristic symbol)
 
Table 1-4 NAND gate truth table

Input


Output


A4


B4


Y4


0


0


1


0


1


1


1


0


1


1


1


0

Logical expression: Y4=(A4·B4)'
Figure 2-4-2 The working principle of CMOS NAND gate
is:
① When A4 inputs low level and B4 inputs low level, Q1 and Q2 are turned on, Q3 and Q4 are turned off, and Y4 outputs high level;
② When A4 inputs low level and B4 inputs high level, Q2 and Q4 are turned on, Q1 and Q3 are turned off, and Y4 outputs high level;
③ When A4 inputs high level and B4 inputs low level, Q1 and Q3 are turned on, Q2 and Q4 are turned off, and Y4 outputs high level;
④ When A4 inputs high level and B4 inputs high level, Q3, Q4 are turned on, Q1, Q2 are turned off, and Y4 outputs low level;
Figure 2-4-3 CMOS NAND gate working principle Figure
2.5 NOR gate
  NOR gate is a superposition combination of OR gate and NOT gate. Only when the inputs are both low level (logic 0), the output is high level (logic 1), otherwise the output is low level (logic 0).
 
Figure 2-5-1 NOR gate logic symbol (rectangular national standard symbol and shape characteristic symbol)
 
Table 1-5 NOR gate truth table

Input


Output


A5


B5


Y5


0


0


1


0


1


0


1


0


0


1


1


0

Logical expression: Y5=(A5+B5)'
Figure 2-5-2 The working principle of CMOS NOR gate circuit
is:
① When A5 inputs a low level and B5 inputs a low level, Q1 and Q2 are turned on, Q3 and Q4 are turned off, and Y5 outputs a high level;
② When A5 inputs a low level and B5 inputs a high level, Q1 and Q4 are turned on, Q2 and Q3 are turned off, and Y5 outputs a low level; ③ When
A5 inputs a high level and B5 inputs a low level, Q2 and Q3 are turned on, Q1 and Q4 are turned off, and Y5 outputs a low level;
④ When A5 inputs a high level and B5 inputs a high level, Q3 and Q4 are turned on, Q1 and Q2 are turned off, and Y5 outputs a low level.
Figure 2-5-3 Working principle of CMOS NOR gate circuit Figure
2.6 XNOR gate
  The XNOR gate (XNOR gate) can be composed of only NAND gates or NOR gates. If the inputs are the same, the output is a high level (logic 1); if the inputs are different, the output is a low level (logic 0).
 
Figure 2-6-1 X-OR gate logic symbol (rectangular national standard symbol and shape characteristic symbol)
 
Figure 2-6-2 X-OR gate implementation
 
Chart 1-6 X-OR gate truth table

Input


Output


A6


B6


Y6


0


0


1


0


1


0


1


0


0


1


1


1Logical

expression: Y6=A6⊙B6=A6·B6 + A6'·B6'
Figure 2-6-3 The working principle of CMOS X-OR gate circuit
is:
① When A6 inputs low level and B6 inputs low level, Q1, Q2, Q3, Q4, Q6, Q9 are turned on, Q5, Q7, Q8, Q10, Q11, Q12 are turned off, and Y6 outputs high level;
② When A6 inputs low level and B6 inputs high level, Q3, Q4, Q5, Q7, Q10, Q12 are turned on, Q1, Q2, Q6, Q8, Q9, Q11 are turned off, and Y6 outputs low level;
③When A6 inputs a high level and B6 inputs a low level, Q1, Q2, Q5, Q8, Q10, Q11 are turned on, Q3, Q4, Q6, Q7, Q9, Q12 are turned off, and Y6 outputs a low level;
④When A6 inputs a high level and B6 inputs a high level, Q5, Q6, Q7, Q8, Q11, Q12 are turned on, Q1, Q2, Q3, Q4, Q9, Q10 are turned off, and Y6 outputs a high level;
Figure 2-6-4 Working principle of CMOS XOR gate circuit Figure
2.7 XOR gate
  The XOR gate (XOR gate) consists of an AND gate, an OR gate and a NAND gate. If the inputs are different, the output is a high level (logic 1); if the inputs are the same, the output is a low level (logic 0).
 
Figure 2-7-1 XOR gate logic symbol (rectangular national standard symbol and shape characteristic symbol)
 
Figure 2-7-2 XOR gate implementation
 
Chart 1-7 XOR gate truth table

Input


Output


A7


B7


Y7


0


0


0


0


1


1


1


0


1


1


1


0

Logical expression: Y7=A7⊕B7=A7·B7' + A7'·B7
Figure 2-7-3 CMOS XOR gate circuit
working principle:
① When A7 inputs low level and B7 inputs low level, Q1, Q2, Q3, Q4, Q8 are turned on, Q5, Q6, Q7, Q9, Q10 are turned off, and Y7 outputs low level;
② When A7 inputs a low level and B7 inputs a high level, Q3, Q4, Q5, Q6, Q10 are turned on, Q1, Q2, Q7, Q8, Q9 are turned off, and Y7 outputs a high level; ③ When
A7 inputs a high level and B7 inputs a low level, Q1, Q2, Q5, Q7, Q9 are turned on, Q3, Q4, Q6, Q8, Q10
are turned off, and Y7 outputs a high level; ④ When A7 inputs a high level and B7 inputs a high level, Q5, Q6, Q7, Q9, Q10 are turned on, Q1, Q2, Q3, Q4, Q8 are turned off, and Y7 outputs a low level;
Figure 2-7-4 CMOS XOR gate circuit working principle diagram
3. Project design
1. Schematic design
  First, open Jialichuang EDA, create a new project and name it [Digital Circuit] Basic Logic Gate Discrete Component Circuit, and name the schematic file: SCH_Basic Logic Gate Discrete Component Circuit.
  Secondly, device selection is carried out. All components here are surface mount devices. Components can be searched in the component library of Jialichuang EDA. Each component has a unique product number in the LiChuang Mall. The power interface uses a 6-pin TYPE-C female socket, and LEDs are used to display and verify the operational relationship of each logic gate.
  Finally, draw the circuit schematic. Each logic gate is drawn according to the module circuit division, and the function of each circuit is indicated. The symbols, truth tables and expressions of each logic gate are added to facilitate understanding and learning.
Figure 3-1-1 SCH_Power input
 
circuit Figure 3-1-2 SCH_PMOS and NMOS
 
circuit Figure 3-1-3 SCH_AND gate
 
circuit Figure 3-1-4 SCH_OR gate
 
circuit Figure 3-1-5 SCH_NOT gate
 
circuit Figure 3-1-6 SCH_NOT gate circuit