Level tester composed of logic gate circuit

In the digital integrated circuit series, logic gate integrated circuits account for a large proportion. The gate circuit is used to form a level tester. The test results are very accurate and the circuit structure is simple. The following figure uses a tester circuit composed of a two-input four-NAND gate CD4093 containing a Schmitt trigger and a common anode LED digital tube LA3621. The two input terminals of the four NAND gates are connected together to form an inverter, where A detects the quotient level, B and C detect the low level, and D detects the CP clock pulse. Cl, VD1, and C2 are used for clock pulse sampling, VD2 and VD3 are isolation diodes, R1, R2, and R3 are current-limiting resistors for the light-emitting pen segment grouping, and VDD and GND are connected to the positive power supply and ground of the circuit under test respectively. If the probe T touches the high level point, after A inversion, the (11) pin outputs a low level, VD2 is turned on, and the digital tube b and c pen segments light up, showing "l", which represents a high level. The high level input by T is inverted twice by B and C, and the ⑩ pin outputs a high level. The 8, d, e, and f pen segments are reverse biased and will not light up. At the same time, due to the DC isolation of C1, the signal will not be transmitted to D, so the g segment will not light up. If T detects a low level, after A is inverted, the (11) pin is high, and VD2 is cut off. At the same time, the signal will not pass through Cl, and the g segment will not light up. After the low level is inverted by B and C, the ⑩ pin outputs a low level, VD3 is turned on, and the a~e segments all light up, showing "0", representing a low level. If T detects a clock pulse, it is equivalent to alternating high and low level inputs, and the digital tube displays "l" and "0" in turn. Because the clock pulse frequency is high, the two characters match to show "0". At the same time, after the clock signal passes through Cl, it is rectified by VD1 and filtered by C2 to generate a high level signal. After D is inverted, the ③ pin outputs a low level, and the g segment lights up, overlapping with the "0" displayed by the above-mentioned low and low levels, showing an "8" shape, representing the CP clock pulse.

The following figure is a tester circuit composed of a six-inverter CD40106 (inverter) containing a Schmitt trigger and a common cathode digital tube LC3011. Its working principle is basically the same as Figure 1. The shared light-emitting pen segments e and f are connected to the positive power supply VDD through the current limiting resistor R3, eliminating the two isolation diodes. As long as the power is turned on, the e and f pen segments will light up. The three inverters B, C, and D are connected in parallel to increase the output driving capability. If 1 detects a high level, the ④, ⑥, and ⑩ pins of B, C, and D are high levels, and the b, c, and g pen segments light up, which together with the normally lit e and 滗 segments display "H", representing a high level. If 1 detects a low level, the E (12) pin is high, the d pen segment lights up, which together with the normally lit e and f pen segments display "L", representing a low level. If 1 detects a clock pulse, the ② pin of F is high, the a pen segment lights up, and the alternating "H" and "L" shapes are restored to an "8" shape, representing a clock pulse.

Analysis and Summary

(1) Since TTL or CMOS gate circuits have definite high and low level input threshold voltages, the level test circuit designed with gate circuits (TTL logic uses TTL gate circuits; CMOS logic uses CMOS gate circuits) does not need to adjust or set the high and low level thresholds, and the measurement results are very accurate.

(2) Using a gate circuit containing a Schmitt trigger has the function of shaping the input signal, making the rising or falling edge of the output signal steep.

(3) Connecting redundant gates in parallel can increase output current and improve load driving capability.

(4) Using capacitor C1 to sample the clock signal can effectively isolate high and low DC level signals, and is simpler to manufacture than using a pulse transformer for sampling.