Brief Introduction of Chip Packaging Technology

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Brief Introduction of Chip Packaging Technology [Copy link]

[Source: Electronic Technology Information Network]

Since Intel designed and manufactured a 4-bit microprocessor chip in 1971, in more than 20 years, the CPU has developed from Intel4004, 80286, 80386, 80486 to Pentium and PentiumⅡ, and the number of bits has developed from 4-bit, 8-bit, 16-bit, 32-bit to 64-bit; the main frequency has increased from several megahertz to more than 400MHz today, close to GHz; the number of transistors integrated in the CPU chip has jumped from 2,000 to more than 5 million; the scale of semiconductor manufacturing technology has increased from SSI, MSI, LSI, VLSI to ULSI. The number of packaged input/output (I/O) pins has gradually increased from dozens to hundreds, and may reach 2,000 at the beginning of the next century. All this is really a revolutionary change. Readers are already familiar with CPUs, such as 286, 386, 486, Pentium, Pentium Ⅱ, Celeron, K6, K6-2... I believe you can list a long list like a treasure. But when it comes to the packaging of CPUs and other large-scale integrated circuits, not many people know about it. The so-called packaging refers to the shell used to install semiconductor integrated circuit chips. It not only plays the role of placing, fixing, sealing, protecting chips and enhancing electrical and thermal performance, but also serves as a bridge between the internal world of the chip and the external circuit - the contacts on the chip are connected to the pins of the package shell with wires, and these pins are connected to other devices through wires on the printed circuit board. Therefore, packaging plays an important role in CPUs and other LSI integrated circuits. The emergence of a new generation of CPUs is often accompanied by the use of new packaging forms. The chip packaging technology has undergone several generations of changes, from DIP, QFP, PGA, BGA to CSP and then MCM, and the technical indicators are more advanced than the previous generation, including the ratio of chip area to package area is getting closer to 1, the applicable frequency is getting higher and higher, the temperature resistance is getting better and better, the number of pins is increased, the pin spacing is reduced, the weight is reduced, the reliability is improved, and it is more convenient to use, etc. The following will explain the specific packaging forms in detail. 1. DIP package In the 1970s, the popular dual in-line package, referred to as DIP (Dual In-line Package). The DIP package structure has the following characteristics: 1. Suitable for PCB perforation installation; 2. Easier to wire the PCB than the TO package; 3. Convenient to operate. The DIP package structure forms include: multilayer ceramic dual in-line DIP, single-layer ceramic dual in-line DIP, lead frame DIP (including glass ceramic sealing, plastic encapsulation structure, ceramic low-melting glass encapsulation). An important indicator to measure the advancement of a chip packaging technology is the ratio of chip area to package area. The closer this ratio is to 1, the better. Taking the CPU with 40 I/O pins plastic encapsulated dual in-line package (PDIP) as an example, its chip area/package area = 3×3/15.24×50=1:86, which is far from 1. It is not difficult to see that the size of this package is much larger than the chip, which means that the packaging efficiency is very low and it takes up a lot of effective installation area. Intel's CPUs during this period, such as 8086 and 80286, all use PDIP packaging. 2. Chip Carrier Packaging 　　In the 1980s, chip carrier packages appeared, including ceramic leadless chip carrier LCCC (Leadless Ceramic Chip Carrier), plastic leaded chip carrier PLCC (Plastic Leaded Chip Carrier), small size package SOP (Small Outline Package), plastic quad flat package PQFP (Plastic Quad Flat Package), and the package structure is shown in Figures 3, 4 and 5. Take the CPU with QFP package of 0.5mm solder area center distance and 208 I/O pins as an example, the outer size is 28×28mm, the chip size is 10×10mm, then the chip area/package area = 10×10/28×28 = 1:7.8, which shows that the package size of QFP is much smaller than that of DIP. The characteristics of QFP are: 1. It is suitable for installation and wiring on PCB using SMT surface mounting technology; 2. The package size is small, the parasitic parameters are reduced, and it is suitable for high-frequency applications; 3. Easy to operate; 4. High reliability. During this period, Intel's CPUs, such as the Intel 80386, used the plastic quad-lead flat package (PQFP). 3. BGA package In the 1990s, with the advancement of integration technology, the improvement of equipment and the use of deep submicron technology, LSI, VLSI and ULSI appeared one after another. The integration of silicon single chips continued to increase, the requirements for integrated circuit packaging became more stringent, the number of I/O pins increased sharply, and power consumption also increased. In order to meet the needs of development, a new variety was added to the original packaging varieties - ball grid array packaging, referred to as BGA (Ball Grid Array Package). As soon as BGA appeared, it became the best choice for high-density, high-performance, multi-functional and high-I/O pin packaging of VLSI chips such as CPUs, north and south bridges. Its characteristics are: 1. Although the number of I/O pins increases, the pin spacing is much larger than QFP, thus improving the assembly yield rate; 2. Although its power consumption increases, BGA can be welded using the controlled collapse chip method, referred to as C4 welding, which can improve its electrothermal performance: 3. The thickness is reduced by more than 1/2 and the weight is reduced by more than 3/4 compared with QFP; 4. The parasitic parameters are reduced, the signal transmission delay is small, and the frequency of use is greatly improved; 5. Coplanar welding can be used for assembly, and the reliability is high; 6. BGA packaging still occupies too much substrate area like QFP and PGA; Intel uses ceramic pin grid array packaging CPGA and ceramic ball grid array packaging CBGA for this kind of highly integrated (more than 3 million transistors in a single chip) and high power consumption CPU chip, such as Pentium, Pentium Pro, PentiumⅡ, and installs a micro exhaust fan on the shell for heat dissipation, so as to achieve stable and reliable operation of the circuit. 4. New packaging technology for the future BGA packaging is more advanced than QFP and better than PGA, but its chip area/package area ratio is still very low. Tessera has made improvements based on BGA and developed another packaging technology called μBGA. With a center distance of 0.5mm for the soldering area, the ratio of chip area to packaging area is 1:4, which is a big step forward compared to BGA. 　　 In September 1994, Mitsubishi Electric of Japan developed a packaging structure with a chip area/package area = 1:1.1, and its package size is only slightly larger than that of a bare chip. In other words, the size of the package is as large as the size of a single IC chip, thus giving birth to a new packaging form, named chip size package, or CSP (Chip Size Package or Chip Scale Package). CSP packaging has the following characteristics: 1. It meets the increasing needs of LSI chip lead pins; 2. It solves the problem that IC bare chips cannot be tested for AC parameters and aging screening; 3. The package area is reduced to 1/4 to 1/10 of BGA, and the delay time is reduced to an extremely short time. Some people once thought that when a single chip cannot reach the integration of multiple chips for a while, can high-integration, high-performance, and high-reliability CSP chips (using LSI or IC) and application-specific integrated circuit chips (ASIC) be assembled into a variety of electronic components, subsystems or systems using surface mounting technology (SMT) on a high-density multi-layer interconnect substrate. This idea gave rise to the multi-chip module MCM (Multi Chip Model). It will have a significant impact on modern computer, automation, communications and other fields. The characteristics of MCM are: 1. The packaging delay time is shortened, making it easy to realize high-speed assembly; 2. Reduce the size and weight of the whole machine/component package, generally reducing the volume by 1/4 and the weight by 1/3; 3. Reliability is greatly improved. With the advancement of LSI design technology and process, as well as the use of deep submicron technology and miniaturization of chip size, people have come up with the idea of assembling multiple LSI chips in a precision multi-layer wiring shell to form MCM products. Another idea has further emerged: integrating the circuits of multiple chips on a large wafer, which has led to a change in packaging from a single small chip level to silicon wafer level packaging, which has led to the system-on-chip SOC (System On Chip) and computer-level chip PCOC (PC On Chip). With the advancement of CPUs and other ULSI circuits, the packaging form of integrated circuits will also develop accordingly, and the advancement of packaging forms will in turn promote the development of chip technology.

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anqi022

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suhongjun

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