dsp28335 IIC Summary

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dsp28335 IIC Summary [Copy link]

1.IIC low-speed synchronous serial half-duplex communication

2.The idle bus is high level, any device outputs low to pull the bus low (the line and relationship of each device)

3.Each device on the IIC bus has a unique address

4.IIC data bit validity regulations: when the clock signal is high, the data line must remain stable, and when the clock signal is low, the high and low level states of the data line are allowed to change. 5. Start signal: SCL is high, SDA changes from high to low. Stop signal: SCL is high, SDA changes from low to high.

6. Each byte is 8 bits long. When data is transmitted, the highest bit is transmitted first. Each transmitted byte must be followed by an acknowledge bit (a total of 9 bits in a frame) (the slave SDA pulls high for non-acknowledgement and pulls low for acknowledgement) (after non-acknowledgement, the host generates a stop signal)

7. The slave can pull SCL low to put the host in a waiting state, and pull SCL high to continue transmitting.

8. Data frame format: The signal on the IIC bus includes both address signals and data signals. A slave address (7 bits) must be transmitted after the start signal; the eighth bit is the data transmission direction 0: send 1: receive

9. The CPU writes data to IICDXR and reads data from IICDRR.

IICDXR->IICXSR->SDA sends

SDA->IICRSR->IICDRR receives

10. Module clock frequency = IIC/(IPSC+1)

Note: The module clock must be configured at 7~12MHZ. The pre-scaler can only be initialized when ISC=0. When the ISR changes from 0 to 1, the frequency generated by the pre-scaler can take effect.

11.IICL in IICCLKL determines the low level time: module clock * (iccl + d)

IICH determines the high level time: module clock * (icch + d)

12.After the CPU reads the interrupt source register IICISRC, it will perform the following steps

[p=26, null, 1) Clear the interrupt source flag bit in the IICSTR register, but do not clear the ARDY, RRDY, and XRDY bits in IICSTR. If you need to clear them, write 1 to the bit. 2) Determine which of the remaining interrupt requests has the highest priority through arbitration, mark it in the IICISRC register, and send the request to the CPU.