Application of Programmable Devices in Radar Data Processing

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Application of Programmable Devices in Radar Data Processing [Copy link]

【Abstract】This paper introduces the structure, characteristics and application of the new programmable logic device CPLD in radar data processing circuits, and focuses on the CPLD implementation methods of four specific circuits. 【Keywords】Data processing, programmable logic device, circuit 1 Introduction　　In recent years, the use of programmable logic devices has had a huge impact on the rapid development of electronic products. It is flexible in design, fast in speed and easy to change, and has been widely used in the design of data processing circuits. There are many advantages to using programmable logic devices to implement digital system design. The most obvious is that the number of devices used in the system is greatly reduced. Secondly, it can save expensive PCB board area, reduce power consumption and shorten debugging time. The biggest advantage is the flexibility of design, which is a feature that discrete components cannot have. Another advantage is that it allows the use of design tools to help you design automatically. 　　High-density field programmable logic devices include complex programmable logic devices (CPLD) and field programmable gate array devices (FPGA). Due to the predictable delay of CPLD, we use CPLD devices in the data processing circuit of single-pulse secondary radar. The characteristics and applications of CPLD devices are explained below. 2 Structure and characteristics of CPLD　　The composition of CPLD can usually be divided into: programmable interconnect, logic block, product-term array, product-term distribution, and input/output cells. 　　Taking Lattice's in-system programmable device ispLSI1032E as an example, according to the chip integration, each chip includes the following components: programmable logic gates: 6000; triggers: 192; input ports: 8; input/output ports: 64; pins: 84. According to the structure 　　, each chip is composed of 4 large blocks (megablock), each large block includes: 8 general logic blocks, 1 output line collection block, 2 input ports, 16 I/O cells, and 1 output strobe enable, as shown in Figure 1. And each general logic block can be divided into 4 blocks according to the internal logic: AND gate array, product term distribution array, reconfigurable trigger, and control function block.　

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　　For ispLSI1032E, 64 I/O units can be directly connected to the I/O port, and can also be programmed as: combinational logic input; register input; latch input; output; tri-state output. And all output terminals can be set to high-level activation or low-level activation. The I/O terminal signal level is compatible with TTL and can provide 4mA drive current or 8mA sink current.
　　ispLSI1032E also has 4 external clock input terminals, allowing users to use external clocks on the chip. In addition, there is a dedicated logic block on the chip, and users can also generate a clock signal by themselves. These clock signals can be used as global clocks.
　　For the convenience of users, CPLD devices also provide a powerful component library. These components are composed of basic elements in the chip, including the component library of the CPLD device itself and the commonly used 74 series component library. Users can also use the components in the above two libraries to construct their own components or component libraries. The use of components in these libraries is exactly the same for users. Just drag them out from the library. The components provided by CPLD itself include the following categories: encoder/decoder; counters, including binary, decimal and Gray code counters; input/output ports, including input, output, input/output bidirectional ports; logic gates, including AND gates, OR gates, NOT gates, NAND gates and NOR gates; multiplexers and distributors; registers, including D flip-flops, JK flip-flops, T flip-flops, D latches, shift registers and various flip-flops with clearing and preset functions.
3 Application of CPLD The
　　original single pulse secondary radar has adopted small and medium-scale integrated circuits, and we need to modify part of the design during the modification. For this reason, we use the new programmable logic device CPLD. Due to the high integration of CPLD devices and their programmability, after the modification, not only the area of the PCB board is reduced to about one-third of the original, but also the redesign and system debugging are completed smoothly, with ideal results. The following are some typical applications of CPLD.
3.1 Counter and comparator circuits
　　Radar measures distance by measuring the time it takes for electromagnetic waves to hit an object and reflect back. For single-pulse secondary radar, the system frequency is 8.276MHz. The current distance counter provides a 15-bit target distance value with an accuracy of 0.01 nautical miles (equivalent to one system clock). The distance listening interval represents the distance range of the target that the system can handle, and it is required to be selectable between 0 and 255 nautical miles. This part of the circuit contains two groups of counters: one group is a 1-nautical-mile carry signal generating counter, which is actually a 102-division counter, that is, a 1-nautical-mile carry signal is sent out every 102 clocks; the other group is a nautical-mile counter, and the 1-nautical-mile carry signal is used as the enable signal of the counter. The count value of the counter corresponds to the number of nautical miles, and the start value and end value of the distance listening interval (i.e., the ranging range) can be preset. By comparing the distance listening interval count value with the preset value, a distance interval mark signal is generated to indicate whether the measured target is within the ranging range. The specific circuit is simplified as shown in Figure 2, where R0~R15 are target distance values, RL0~RL7 are distance listening interval count values, the distance listening interval is 5~250 nautical miles, and RLI is the distance interval flag. These circuits are implemented using CPLD devices, using less than half of the resources of an ispLSI1032E.
3.2 Long delay circuit
　　The reply signal of the secondary radar consists of 12 code pulses and a frame pulse pair (F1, F2). The interval between the frame pulse pairs is 168 system clocks. The 12 code pulses and 1 X pulse (not used yet) are evenly spaced between the frame pairs, that is, there is a code pulse or frame pulse every 12 system clocks. If a pulse delayed by 168 clocks and a pulse that is not delayed exist at the same time, it can be considered that there is a frame. Of course, the actual judgment is much more complicated, but the basic principle

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The same, its simplified circuit is shown in Figure 3: 93422 is a 256×4-bit static RAM, its address is generated by a 168-division counter, whenever the RAM address changes, the content of the address unit is read out first, and then the new content is written. Since the address counter is divided by 168, reading a certain signal is delayed by 168 clocks than writing the signal, so by comparing the input and output RAM signals, it can be determined whether there is a frame, and the delay line here ensures that when the address changes, the RAM is read first and then written. But it should be noted that there is no RAM and delay line in the CPLD device, so a static RAM 93422 and a delay line are needed here, and other circuits can be completed by the CPLD device.
3.3 Short delay circuit
　　Short delay circuit is often used in secondary radar to achieve the purpose of timing coordination. For example, the side lobe suppression signal RSLS needs to be delayed by 5 clock cycles. In addition to using address counter and RAM to form a delay circuit like the long delay circuit, a simpler method is to use 4×4 register stack and frequency divider to form it, as shown in Figure 4: the read and write enable of the register stack is used as the high address and low address of the register stack after two-frequency division and four-frequency division, respectively, and the read enable of the register stack is generated after the write enable is delayed by 5 clock cycles. Therefore, the same signal is exactly 5 clock cycles from writing to reading the register.
3.4 Discrimination criterion circuit
　　In the secondary radar, the answer of the aircraft is judged according to certain criteria. This criterion is somewhat complicated to implement, because there are many conditions for making a judgment, and it is required to complete the judgment within 1.45μs. Therefore, it can only be completed through high-speed hardware circuits. Here, PROM can be used to implement various judgments. The address is the condition for judgment, and the content is the result of judgment. The following takes the discrimination of military response as an example to explain its working principle: Military response is a special response, which is composed of two consecutive frame pairs separated by 3 code pulse positions (36 system clocks), while military warning response is composed of four consecutive frame pairs separated by 3 code pulse positions
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If a response has an SPI code pulse, and this code pulse is the F1 frame of the next response, it can be determined as a military response; if two military responses appear consecutively, it can be determined as a military warning response. The PROM is judged to have a capacity of 128×4 bits. The address is composed of the F1 frame pulse and SPI pulse of four consecutive responses respectively, and the content is the judgment result. If two responses constitute a military response relationship, the outputs of these two responses are both "1". Therefore, when two consecutive responses are marked, it can be determined that there is a military response. When four consecutive responses are marked, it can be determined that there is a military warning response. According to the above criteria, Table 1 can be obtained. It can be realized by a BPROM chip 82S131, but with the changes of the times, BPROM chips have been basically discontinued and it is difficult to find sources. For this reason, we use CPLD devices to realize it. After simplifying Table 1 with a card diagram, the output logic expression is obtained:
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　　The above combinational logic is very easy to implement in CPLD devices. The specific circuit is shown in Figure 5.
4 Conclusion
　　The use of programmable devices not only greatly simplifies the layout of PCB boards, but also compresses dozens or even hundreds of general-purpose IC chips into a CPLD chip. More importantly, programmable devices can modify circuit design at any time without changing the input/output pins, which greatly improves the design efficiency.

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The product design cycle is shortened; and while the peripheral circuit remains unchanged, a new function can be realized by replacing a CPLD chip. This feature is especially important for developing serialized products.

　　　References　　

1 Lattice Semiconductor Corp. ，ISP Data Book． Lattice Semiconductor Corp． ，1994
2 Song Wanjie, Luo Feng, Wu Shunjun ed. CPLD Technology and Its Applications. Xi'an: Xi'an University of Electronic Science and Technology Press, 1999,
9 3 Jiang Xuan, Zang Chunhua ed. Digital System Design and PLD Application Technology. Beijing: Electronic Industry Press, 2001, 11