Application of complex programmable logic devices in communication data transmission

1 Overview

With the rapid development of large-scale integrated circuits and single-chip microcomputers, complex programmable logic devices (CPLDs) have the advantages of flexible use, high reliability and powerful functions, and have been widely used in the design of electronic products. CPLD can realize in-system programming, repeated multiple times, and is also compatible with the test stimulus terminal and boundary scan capability of the IEEE1149.1 (JTAG) standard. Using CPLD devices for development can not only improve the integration, reliability and scalability of the system, but also greatly shorten the product design cycle. Because CPLD uses a continuous connection structure, it is easy to predict the delay, making the circuit simulation more accurate. CPLD is a standard large-scale integrated circuit product that can be used in the design of various digital logic systems. In recent years, with the use of advanced integration technology and mass production, the cost of CPLD devices has continued to decline, and the integration density, speed and performance have been greatly improved. Such a chip can realize a complex digital circuit system; coupled with easy-to-use development tools, it brings great convenience to design modifications.

The laboratory has designed and developed a wireless data receiving platform with uplink and downlink rates of up to 1Mbps. The RF part uses Maxim's RF chip set, the baseband part uses the OMAP platform, the baseband RF interface uses ADI's mixed signal front-end (MxFE™) baseband transmission chip AD9861, and the system logic control and data buffering use ALTERA's CPLD EPM240GT100C3.

2 EPM240GT100C3 functions and overall requirements

EPM240GT100C3 needs to complete the timing control of AD9861, data cache between AD9861 and OMAP, and provide the control signals required by the network port chip LAN91C93. Among these functions, the most important one is the data cache function. In order to correctly implement the cache function, it is necessary to ensure that the cached I and Q data are not lost, reversed, or out of phase, and at the same time ensure that the data is written first and read later. According to this idea, combined with the interface timing on both sides, the read and write addresses and read and write clocks are correctly configured to complete the required functions.

3 Detailed design of CPLD program

The main function of CPLD is to complete data caching and generate some clock control signals. Its functional block diagram is shown in Figure 1, which mainly includes dual-port RAM storage unit, clock and control signal generation unit, OMAP side address generation unit, and AD9861 side address generation unit.

Figure 1 CPLD functional block diagram

3.1 Design Method of Dual-Port RAM

Because both OMAP and AD9861 have read and write operations, dual-port RAM (DPRAM) was selected as the data cache. Due to the limited logic and wiring resources inside the CPLD and the lack of an independent DPRAM area, the DFF can only be used to complete the cache function, which limits the size of the DPRAM. Because the system requires each DMA interrupt to read and write 8 data, in order to reduce the possibility of read and write conflicts and minimize the use of FF resources, a 16×8 dual-port RAM buffer equivalent to two 8×8 ping-pong buffers was finally used. The external interface of the DPRAM is shown in Figure 2:

Figure 2 DPRAM external interface

Among them, dina and douta are connected to the data line of OMAP, dinb and doutb are connected to the data line of AD9861, and addra and addrb are the internally generated read and write addresses. Wr_rd_en controls the direction of reading and writing, and is connected to TX_RX, that is, when Wr_rd_en＝'1', it is transmitting, the data is written by OMAP, read by AD, and the data flows from dina->doub; when Wr_rd_en＝'0', it is receiving, the data is written by AD, read by AD, and the data flows from dinb->doua; wrclk switches between four clocks, which are 3.2768M, 6.4M, 75M, and 84M, respectively, and are controlled by the high and low levels of TX_RX and V_D_SEL signals. In order to reduce the use of wiring resources, the read clock is not used when reading, but the data on the addra and addrb addresses are directly output, because addra and addrb are originally synchronized with the read and write clock. [page]

3.2 Clock Generation

The CPLD input clocks include 16M clock from RF, 32.768M clock from external crystal oscillator and 75M clock CLK from OMAP interface. Among them, 16M clock is used to generate 3.2M and 6.4M conversion clocks required by AD9861 for data application, 32.768M clock is used to generate 1.6384M and 3.2768M clocks required by AD9861 for voice application, and 8K and 2.048M clocks required by CODEC AIC1110. SDCLK ​​can be used as the main clock for OMAP reading and writing, but it must be used with CAS signal as read and write permission. In order to save wiring resources, CAS is directly used as write clock and address generation on OMAP side without read and write permission, and SDCLK ​​is used to generate some synchronization pulses. In addition to being output to external chips, these generated clocks are also used as clocks for address generation inside CPLD. The 3.2M and 6.4M clocks are generated by counting the 16M clock from 0 to 4, and the counter is cleared by reset and ad_da_enable. The lowest bit of the modulo 5 counter is 6.4M, and the second lowest bit is 3.2M clock. This clock generation method only requires three DFFs, saves logic resources, and does not generate glitches, but the generated clock duty cycle is not 50%. Practice has proved that AD9861 can work normally in low-speed applications. The system clock timing is shown in Figure 3.

Figure 3 Clock timing

The method for 1.6384M and 3.2768M clocks is the same, except that the 32.768M clock needs to be divided by 20. Similarly, the counter is cleared by reset and ad_da_enable. In this way, the second bit of the modulo 20 counter is 3.2768M, and the third bit is 1.6384 clock. The timing is similar to the above figure and is not given here.

These four clocks are assigned to the main clock ADA_CLK of AD9861 in time-sharing mode. Which clock is assigned to ADA_CLK is controlled by the transceiver switching signal TX_RX and the voice and data selection signal V_D_SEL. When TX_RX='0' and V_D_SEL='0', the clock output to ADA_CLK is 1.6384M; when TX_RX='1' and V_D_SEL='0', the clock output to ADA_CLK is 3.2768M; when TX_RX='0' and D_SEL='1', the clock output to ADA_CLK is 3.2M; when TX_RX='1' and V_D_SEL='1', the clock output to ADA_CLK is 6.4M.

In order to further save resources, it is possible to consider sharing the modulo-5 and modulo-20 counters. The solution is shown in Figure 4. BIT1 and BIT2 are the required clocks. At this time, the front-end clock source is selected by V_D_SEL, and the selection output of BIT1 and BIT2 is controlled by TX_RX.

Figure 4: Clock generation scheme for modulo-5 and modulo-20 counters

The 2.048M clock is generated by dividing the 32.768M clock by 16. The reset of the counter is controlled by reset and voice enable audcken. The high bit of the modulo 16 counter is the 2.048M clock. The 8K clock is obtained by dividing the 2.048M clock by 256.

3.3 Address Generation

When using dual-port RAM as data cache, there are two parts of address generation circuit: OMAP side address generation circuit and AD9861 side address generation circuit. The AD9861 side address generation circuit and the OMAP side address generation circuit are roughly the same, but because these two address generators are used at the same time, they cannot be reused. The block diagram of the OMAP address generator is as follows:

Figure 5 OMAP address generator

The CAS clock is only responsible for counting the lower 3 bits of the address, and the highest bit selects one of the two 8×8 RAMs. To prevent adda and OMAP from reading and writing the same RAM at the same time, the high address line on the OMAP side is set to the inverse of the highest bit of the address on the AD9861 side. Function of DMA request clear signal: Every time a DMA request is triggered on the AD9861 side, a DMA request clear signal is generated to reset the address generator on the OMAP side to avoid confusion in the OMAP read and write address due to some false triggering. The address generator on the AD9861 side is as follows:

Figure 6 AD9861 side address generator

The lower 3 bits of the 4-bit address bus are used to select the 8 addresses in the same RAM, and the highest bit is used to select one of the two 8×8 RAMs. The transmit/receive switching signal is used to clear the address generator when the transmit/receive switching occurs, and reset the address bus error caused by the logic mis-trigger. [page]

3.4 LAN control signal generation

lan91c93 is an embedded Ethernet controller, which together with OMAP constitutes an embedded Ethernet network interface card. OMAP uses asynchronous FLASH interface timing to access lan91c93. Since lan91c93 does not have a chip select input, the chip select and read/write signals of the flash are processed and output to lan91c93. OMAP allocates CS1 space to lan91c93. When nFLASH_CS1 is low, nFLASH_WE and nFLASH_OE are output to nLAN_WE and nLAN_OE, otherwise nLAN_WE and nLAN_OE are high. At the same time, the LAN_RDY signal is transparently transmitted to OMAP through CPLD to notify OMAP that lan91c93 is ready for data exchange.

4 Simulation and measurement

4.1 Data receiving state simulation

Set V_D_SEL to high and TX_RX to low, indicating that it is in the data receiving state. Generate the required clock and reset signal according to the timing relationship; generate data on the AD9861 data line to simulate the output of AD; generate ADA enable input control signal AD_DA_ENABLE; SDRAM CAS signal, etc. As shown in the figure below, DINB is the data on the AD9861 data line, WRCLK is the internally generated 6.4M latch clock, which is used to write the data on the DA data line into the dual-port RAM. The address ADDRB on the AD9861 side is obtained by counting the falling edge of the write clock WRCLK. When ADDRB is 8 or 0, a DMA interrupt is generated, triggering OMAP to read the data to the DSP 's MEMORY through the EMIFF interface for processing. Each DMA request reads 8 data and generates 8 low-pulse CAS signals. The number of CAS pulses is counted to obtain the lower 3 bits of the OMAP side address. The highest bit is obtained by inverting the MSB of ADDRB, which can avoid read-write conflicts. It can be seen that the output data of AD can be correctly reproduced on the EMIFF interface data line of OMAP and read correctly by OMAP.

Figure 7 Data receiving status signal timing

4.2 Data transmission state simulation

Set V_D_SEL to high and TX_RX to high, indicating that it is in the data transmission state. Generate the required clock and reset signal according to the timing relationship; generate data on the EMIFF interface data line, simulate the transmission data output by OMAP; simulate and generate the ADA enable input control signal AD_DA_ENABLE; SDRAM CAS signal, etc. As shown in the figure below, ADA_CLK is an internally generated 6.4M clock, which is output as the main clock of the DA conversion of ad9861. Count the rising edges of ADA_CLK to get the address ADDRB on the AD9861 side. When ADDRB is 8 or 0, a DMA interrupt is generated, triggering OMAP to output the transmission data to the EMIFF interface data bus through the EMIFF interface. Each DMA request writes 8 data and generates 8 low-pulse CAS signals. Count the number of CAS pulses to get the lower 3 bits of the address on the OMAP side. The highest bit is obtained by inverting the MSB of ADDRB, which can avoid read-write conflicts. DINA is the data on the EMIFF interface data line. The falling edge of the CAS delay signal is used to latch DINA, which meets the SDRAM write timing of EMIFF and can correctly write the data into the dual-port RAM. DOUTB is the data output to DA. At the same time, a transmission synchronization signal TX_SYNC is generated according to the timing requirements to indicate the transmitted I and Q. The rising edge of ADA_CLK is used for sampling, which can be sampled just in the middle of DOUTB and TX_SYNC to ensure data stability.

Figure 8 Data transmission status signal timing

4.3 Data measurement results

The recorded spectrum, time domain waveform and constellation diagram are as follows. The spectrum is 250K, which is consistent with the frequency deviation set by the signal source. The time domain waveform I lags behind Q by 90 degrees, and the maximum value of I corresponds to the zero point of Q. The orthogonality of the two is guaranteed, which is also proved by the fact that the constellation diagram is a circle.

Figure 9 Received signal spectrum

Figure 10 Time domain waveform of received signal

Figure 11 Received signal constellation diagram