What is a totem pole and how does it differ from an open-drain circuit?

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What is a totem pole and how does it differ from an open-drain circuit? [Copy link]

In TTL integrated circuits, the output with a pull-up transistor is called a totem pole output, and the output without a pull-up transistor is called an OC gate. Because TTL is a three-level gate, the totem pole is two transistors connected in push-pull mode. So push-pull is a totem. Generally, the totem output is 400UA for high level and 8MA for low level.+++++++++++++++++++++++++++++++++++++++++++++++ The unused input terminals of CMOS devices must be connected to high or low level, because CMOS is a high input impedance device, and ideally there is no input current. If the unused input pins are left floating, it is easy to sense interference signals, affecting the logic operation of the chip, and even static electricity accumulation will permanently break down the input terminal, causing the chip to fail. In addition, only 4000 series CMOS devices can work under 15V power supply, 74HC, 74HCT, etc. can only work under 5V power supply, and now there are CMOS logic circuit chips that work under 3V and 2.5V power supply. CMOS level and TTL level: CMOS logic level has a relatively large range, ranging from 3 to 15V. For example, when the 4000 series is powered by 5V, the output is high when it is above 4.6V, and the output is low when it is below 0.05V. The input is high when it is above 3.5V, and low when it is below 1.5V. For TTL chips, the power supply range is 0 to 5V, and 5V is common. For example, when the 74 series is powered by 5V, the output is high when it is above 2.7V, and low when it is below 0.5V. The input is high when it is above 2V, and low when it is below 0.8V. Therefore, there is a level conversion problem between CMOS circuits and TTL circuits, so that the level domain values of the two can match. Some concepts about logic levels: To understand the content of logic levels, we must first know the meaning of the following concepts: 1: Input high level (Vih): The minimum input high level allowed when the input of the logic gate is high. When the input level is higher than Vih, the input level is considered to be high. 2: Input low level (Vil): The maximum input low level allowed when the input of the logic gate is low. When the input level is lower than Vil, the input level is considered to be low. 3: Output high level (Voh): The minimum value of the output level when the output of the logic gate is high. The level value of the logic gate's output when it is high must be greater than this Voh. 4: Output low level (Vol): The maximum value of the output level when the output of the logic gate is low. The level value when the output of the logic gate is low must be less than this Vol. 5: Threshold level (Vt): Digital circuit chips all have a threshold level, which is the level when the circuit can just barely flip the action. It is a voltage value between Vil and Vih. For the threshold level of CMOS circuits, it is basically half of the power supply voltage. However, to ensure stable output, it is necessary to require that the input high level > Vih and the input low level For general logic levels, the relationship between the above parameters is as follows: Voh > Vih > Vt > Vil > Vol 6: Ioh: Load current when the logic gate output is high (source current). 7: Iol: Load current when the logic gate output is low (sink current). 8: Iih: Current when the logic gate input is high (sink current). 9: Iil: The current when the logic gate input is at a low level (pull current). The output of the gate circuit is not connected to a load resistor in the integrated unit but is directly led out as the output terminal. This form of gate is called an open gate. The open TTL, CMOS, and ECL gates are called open collector (OC), open drain (OD), and open emitter (OE) respectively. When using them, you should check whether to connect a pull-up resistor (OC, OD gate) or a pull-down resistor (OE gate), and whether the resistance value is appropriate. For an open collector (OC) gate, the pull-up resistor RL should satisfy the following conditions: (1) RL < (VCC-Voh)/(n*Ioh+m*Iih) (2) RL > (VCC-Vol)/(Iol+m*Iil) Where n: the number of open gates of the wired-AND; m: the number of driven input terminals. 10: Commonly used logic levels ·Logic levels: TTL, CMOS, LVTTL, ECL, PECL, GTL; RS232, RS422, LVDS, etc. ·The logic levels of TTL and CMOS can be divided into four categories according to the typical voltage: 5V series (5V TTL and 5V CMOS), 3.3V series, 2.5V series and 1.8V series. ·5V TTL and 5V CMOS logic levels are universal logic levels. ·Logic levels of 3.3V and below are called low voltage logic levels, and the commonly used ones are LVTTL levels. ·There are two types of low voltage logic levels: 2.5V and 1.8V. ·ECL/PECL and LVDS are differential input and output. RS-422/485 and RS-232 are serial port interface standards. RS-422/485 is differential input and output, and RS-232 is single-ended input and output.