Three-phase bidirectional SiC bridgeless totem pole inverter/PFC development board

# Three-phase bidirectional SiC bridgeless totem pole inverter/PFC development board

! [actual picture.jpeg] ![hardware block diagram.png]
This project is a fully functional three-phase/single-phase bidirectional AC-DC inverter Experimental platform, designed to provide learners and researchers with a reliable and easy-to-operate environment for studying and experimenting with forward power factor correction (PFC) operation and reverse inverter equipment.
The design of the experimental platform equipment focuses on providing users with a complete solution that includes all necessary hardware and software functions to support learning and experimentation with power electronic equipment in a real environment. This set of equipment adopts a three-phase AC-DC configuration, which is a common system structure in the field of power systems and power electronics. It can simulate the real-life data center power supply front stage, two-way vehicle charger, inverter, SVG/APF, high-power wireless Brush motor driver etc.
Learning and experimentation of forward PFC operations is one of the main functions of this experimental platform. Power factor correction is an important concept in power electronics. By controlling the phase and amplitude of the input current to synchronize with the input voltage, the efficiency of the equipment can be maximized and energy loss reduced.
On the other hand, the experimental platform also supports the learning and experimentation of reverse inverter equipment. Inverter is a device that converts DC power into AC power. It is widely used in power systems, such as solar photovoltaic power generation, electric vehicle inverter, etc.
In terms of device selection, this design tries to choose domestic devices as much as possible. These devices not only have stable procurement channels, but also have relatively low prices. Their experimental performance is stable and reliable enough to meet experimental needs.


B station video link: https://www.bilibili.com/video/BV1PP411e7AZ
# **Warning**

1. This design is only suitable for laboratory environment and cannot be used as a final product for ordinary consumers.
2. This design is limited to use by professional engineers and technicians who have experience in operating high-voltage electronic and mechanical components and can properly handle related risks.
3. Attention! There is a **high voltage** section inside the circuit board. Careless handling or misuse may cause electric shock, fire or personal injury. When using this equipment, you must maintain a high degree of vigilance and take appropriate protective measures to prevent possible personal injury or property damage.
4. It is strictly prohibited to power on this design without supervision.
5. To ensure safety, it is strongly recommended to use isolation test equipment equipped with overvoltage and overcurrent protection functions. It is the user's responsibility to ensure that the voltage and isolation requirements are fully understood and mastered before powering the board or performing simulations. **After power is supplied, please do not touch this design or any components connected to it**.
6. Warning: **The surface may be hot! **Touch may cause burns. Do not touch! When the circuit board is powered on, some components may heat up above 55°C. Users should avoid touching circuit boards during operation or immediately after operation as the surface may be dangerously hot.
7. **The design is for 110v system. It is strictly prohibited to use voltage exceeding the rated voltage for power supply**

## About hardware

### The control board

first welds the chip to ensure there is no short circuit, then welds the LDO, clock circuit, etc. to ensure that the crystal oscillator waveform is normal. After burning the code, there is a built-in 2900mv reference output at the Vref pin.

### In the low-voltage scenario of the half-bridge board,

the gate capacitors of MOSFETs connected in parallel are empty soldered, returned and inspected, and the Miller clamp circuit is recommended for soldering. After welding, first apply 12v power, and the current should not exceed 100ma. After the output of the isolated power supply is normal, the voltage will be increased to 24v. Check whether the voltage at each point is normal.

Using SIC driver requires 24V, and the 12V marked on the schematic diagram is wrong.

**Note that the GH GL label silk screen of this version of the switch half-bridge is reversed, please pay attention to the flying wire correction**

**It is strongly recommended to test the relevant signals according to the debugging process before powering on the system! **![image-20230604183301656.png]

###

Weld the DCDC circuit and the LDO of AVDD and DVDD to the base plate, supply 12v, measure the voltage

and weld the signal conditioning op amp, TL432 bias reference (please modify the voltage divider resistor, the schematic diagram is not accurate ) 1450mv, measure whether the voltage at each point is normal.

Weld the isolated power supply and measure whether the isolated power supply voltage output is normal.

Finally, weld five isolation op amps and power on. The current of the whole board should not exceed 150ma. The isolation op amp generates slight heat.

**Note: **Under the 0 input condition, the input bias current of the isolation op amp affects the high impedance distribution. The piezoresistor network causes the overall output voltage to have an upward offset of about a few hundred mv. This offset will cause the bus voltage detection range to be non-symmetrical. This is a BUG, ​​and the solution should be replaced and redesigned later. Isolated op amps that detect current do not have this problem. This DC offset should be calibrated in a subsequent software program.

**Note that the PWM drive signal CH CL of phase C of this version of the backplane circuit is reversed, please pay attention to the flying lead correction! **


![image-20230604183419461.png] ###

Just pay attention to the safety distance between the LCL filter and the relay. The current of a relay is about 50ma.

The final parameters of the LCL filter used in real life may be different from the design parameters. The final parameters are:

Network Side inductor: 080-125 FeSiAl magnetic ring 1.0 wire diameter 10A100uH

filter capacitor: X2 safety capacitor 275V 2.2uF Uxin electronic

filter inductor: Huawei 3kW communication power supply disassembled flat line inductor. 500uH, saturation current unknown, estimated 15A?

The above parameters are for reference only! Please calculate and modify it yourself.

## About the software

system, it has input over-current detection, output over-voltage and over-current detection. Its protection function uses the internal hardware of the controller to shut down and lock the PWM wave. There is no guarantee that the protection can be triggered stably under any circumstances. Please refer to the design document for specific protection design.

Although the sampling circuit is fully isolated, it is still strongly recommended not to get close to it or touch any exposed part of the system while the system is running! Under no circumstances is it allowed to use non-isolated methods to measure components on the high-voltage side**!

**Be sure to use a low-voltage DC power supply and perform open-loop inversion to correct the bug in the hardware where the gate drive signal is reversed! **

**Be sure to use a low-voltage DC power supply and perform open-loop inversion to correct the BUG of the gate drive signal being reversed on the hardware! **

**Be sure to use a low-voltage DC power supply and perform open-loop inversion to correct the BUG of the gate drive signal being reversed on the hardware! **

For specific software debugging methods, please refer to

[https://www.ti.com.cn/tool/cn/TIDA-01606](https://www.ti.com.cn/tool/cn/TIDA-01606)

The software is designed based on keil+stm32cubemx+LL library.
After downloading and decompressing, you cannot directly compile, download and run. Please modify the system parameters according to the warnings/errors after compilation!

## other

Due to my limited energy, this hardware design draft is the first version. The bugs encountered may not be described in detail one by one. I also do not have the time and energy to correct the bugs and then re-print the board for verification.

The software and hardware of this design refer to the TI/ST software and hardware design. For the copyright description of the library, please refer to its official website description. **This design can only be used for learning purposes, please do not use it for commercial use! **

The calculation formulas in the design documents have not been studied in detail. for reference only.

At room temperature of 27 degrees, the system temperature should not exceed 60 degrees when running 750W for ten minutes.

### Regarding interrupts

, the code provided in this design has certain similarities and differences with TIDA-01606. In addition to the differences in MCU register control, a more important point is to control the ISR triggering method: HRTIM triggers ADC sampling at a specific time -> The interrupt is triggered after the conversion of all injection groups in ADC1 is completed, and the loop control code is executed within the interrupt. This project uses PA6 to detect the execution frequency and time in control interrupts. The high level is the interrupt response process. In LAB7, the interrupt CPU time is about 75%. The default execution is the same frequency as PWM, which is 42525Hz.

After using STM32cubeMX to regenerate the code, please note that the control macro using CCMRAM in CoreSrcstm32g4xx\_it will be overwritten. Please ensure that the interrupt is modified correctly, especially in the ISR ADC1\_2\_IRQHandler, this ISR runs the interrupt control code.

ADC1\_2\_IRQHandler

HRTIM1\_FLT\_IRQHandler

SysTick_Handler

ADC4_IRQHandler

DMA2\_Channel5\_IRQHandler

The default PWM mapping is:

#define PFC\_PHASE\_A\_TIMER LL\_HRTIM\_TIMER\_F
#define PFC\_PHASE\_B\_TIMER LL\_HRTIM \_TIMER\_E
#define PFC\_PHASE\_C\_TIMER LL\_HRTIM\_TIMER\_A
#define PFC\_PHASE\_N\_TIMER LL\_HRTIM\_TIMER\_B

### Default sampling trigger setting

Default ADC mapping is:

phase current And bus current collection - ADC1

phase current: ADC\_Injected\_ConversionMode trigger source: HRTIM ADC trigger 2 event, trigger conversion of all rule groups at one time, sampling period is 6.5 clock cycles.

Phase A current——PA0——Injection group RANK1

Phase B current——PA1——Injection group RANK2

Phase C current——PA2——Injection group RANK3

Bus current: ADC\_Regular\_ConversionMode Trigger source: HRTIM ADC trigger 3 event, Scan conversion mode, enable 4 times oversampling, use DMA1 CH1 to transfer the results to the memory, the sampling period is 12.5 clock cycles

Bus current - PA3 - Rule group RANK1

grid and bus voltage collection -> ADC2

phase voltage: ADC\_Injected \_ConversionMode trigger source: HRTIM ADC trigger 2 event, trigger conversion of all rule groups at one time, sampling period is 6.5 clock cycles.

Phase A current——PC0——Injection group RANK1

Phase B current——PC1——Injection group RANK2

Phase C current——PC2——Injection group RANK3

Bus voltage: ADC\_Regular\_ConversionMode Trigger source: HRTIM ADC trigger 3 event, Scan conversion mode, enable 4 times oversampling, 2-bit displacement, use DMA1 CH2 to transfer the results to the memory, the sampling period is 12.5 clock cycles.

High-side capacitor voltage - PA7 - Rule group RANK1

low-side capacitor voltage - PA4 - Rule group RANK2

temperature and internal reference voltage acquisition ADC4

ADC\_Injected\_ConversionMode trigger source: software trigger, one trigger converts all rule groups, enables 16 times oversampling, 4bit displacement, and the sampling period is 640.5 clock cycles.

### fault path

// OC_AC --> FAULT 1
// GATE_F --> FAULT 2
// OV_DC --> FAULT 3
// OC_DC --> FAULT 4