Protection and recovery of program interruption in TMS320C2x

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Protection and recovery of program interruption in TMS320C2x [Copy link]

The following is a TMS320C2x program that generates a 10KHz positive pulse on the XF pin. PRD .set 3 IMR .set 4. ． text LDPK 0 LALK #999 SACL PRD ；Set timer period register = 999 LACL #8 0R IMR SACL IMR ；Open timer interrupt RXF ；XF set low EINT : open interrupt LO0P: B LOOP Copy code ；Timer interrupt service routine TINT_ISR: SXF ；XF set high SXF ；XF set low EINT ；Open interrupt RET ；Interrupt return. Copy code The timer of TMS320C5X adds some control functions based on TMS320C2X. By setting the timer control register TCR, the timer can be started and stopped, and the timer division ratio can also be set. The interrupt frequency of the timer is f = CLKOUT1/[(TDDR+1)(PRD+1)] Copy code In the formula, TDDR is the division ratio, and PRD is the value of the period register. C. Protection and recovery of interrupts The status protection and recovery of the interrupt program can be performed according to the usage of the registers in the interrupt program. However, when protecting the two status registers ST0 and ST1, special attention must be paid to the order of recovery. TMS320C2X uses special instructions SST0 and SST1 to protect ST0 and ST1 registers, and uses LST0 and LST1 to restore. If indirect addressing is used for protection, the order of protection and recovery is irrelevant. However, if direct addressing is used, attention must be paid to the order of recovery. The following is the correct method of TMS320C2x interrupt protection and recovery when direct addressing is used. In the program, TST0, TST1, etc. are all storage units defined in page 0 of the data space. ISR_SUB: SST0 TST0 ; Save ST0 to TST0 cells (force DP = 0) SST1 TST1 ; Save ST1 to TST1 cells (force DP = 0) LDPK 0 ; DP = 0 SACL TACCL ; Save upper 16 bits of ACC SACH TACCH ; Save lower 16 bits of ACC, " ZAIS TACCL ; Restore lower 16 bits of ACC ADDH TACCH : Restore upper 16 bits of ACC LST1 TST1 ; Restore ST1 LST0 TST0 ; Restore ST0 EINT : Interrupt enable. RETI ; If the order of restoration is reversed, that is, the LST0 instruction is executed first and then the LST1 instruction is executed, the data page pointer DP cannot be restored correctly. This is because the data page pointer DP is in the status register ST0. When LST0 is executed, the current data page is actually changed to the DP value in ST0. When LST1 is executed again, DP is not forced to be set to 0 like SST1. Therefore, the data page is wrong, and the restored ST1 content is incorrect. D. Relocation of TMS320C5X vector table The address of the interrupt vector table of TMS320C2x is fixed at a position starting from the address o in the program space. Fixed interrupt vector table address may cause some trouble in some cases. For example, when the system adopts the memory configuration of low-speed EPROM plus high-speed RAM, although the program can be moved from EPROM to high-speed RAM when the system is powered on, the address of the interrupt vector is fixed. Therefore, when the system generates an interrupt, the jump instruction at the interrupt vector address will have to run several more instruction cycles. TMS320C5x has made improvements so that the address of the interrupt vector table can be relocated by the program. The vector address can be relocated to the beginning of any 2K word page in the program space, such as 800H. The relocation method is to set the corresponding value in the IPTR field of the PMST register. When reset, IPTR = 0, the first address of the interrupt vector table is 0H. If IPTR = 1, the first address is 800H. After reset, execute the following instruction to relocate the vector table address to 800H: OPL #800H,PMST Copy the code After executing the above instructions, the interrupts generated later will obtain the interrupt vector from the new vector table. For example, the vector address of the timer interrupt after reset is BH, while the new vector address is 808H. E. Software Implementation of Wait State Generation in TMS320C5X In order to interface with low-speed memory or I/O devices, TMS320C2x needs to use hardware wait state generator, which complicates the hardware design. TMS320C5X supports hardware wait state generation, and can also use software to control the generation of wait state, thus simplifying the hardware design and saving system volume. The software programmable wait state generator is controlled by two 16-bit wait state registers PDWSR and IOWSR and a 5-bit control register CWSR. F. Software Migration from TMS320C2x to TMS320C5X The instruction set of TMS320C2x is upward compatible at the source code level. Therefore, in principle, the program of TMS320C2X can be run on TMS320C5x after being reassembled by the assembler of TMS320C5X. However, since the TMS3210C5x is different from the TMS320C2x in terms of serial port, timer and global control, some necessary modifications must be made when porting the software from TMS320C2x to TMS320C5X. For example, Table 2.2 lists the modifications to some instructions related to serial port settings. In addition, it must be noted that the addresses of some registers are also different. TMS320C25 TMS320C50 RFSM APL #0FFF7H,SPC SFSM OPL #8,SPC RTXM APL #0FFDFH,SPC STXM OPL #020H,SPC FORT0 APL #0FFFBH,PC FORT1 OPL #4,SPC