Application of interrupts in TMS320C54x series DSP

　　Interrupts are the soul of embedded chips. This is because most embedded systems have high requirements for real-time performance, that is, they must respond extremely quickly to events. Interrupts have higher execution efficiency than software query methods. In TI's TMS320C54x series (hereinafter referred to as the C54x series) DSP, a good interrupt mechanism is also provided.

       1 Interrupt mechanism in C54x

　　The interrupt signal is essentially a signal driven by hardware or software, which enables the DSP to suspend the executing program and enter the interrupt service routine (ISR). In the most typical DSP system, if the A/D converter needs to send data to the DSP, or the D/A converter needs to take data from the DSP, it sends a request to the DSP through a hardware interrupt.

　　The C54x series DSP supports software interrupts and hardware interrupts. Software interrupts are triggered by instructions (INTR, TRAP, RESET), and hardware interrupts are triggered by peripheral devices. Hardware interrupts are actually divided into two categories: one is triggered by the DSP's off-chip peripherals (such as the A/D converter), and the other is triggered by the DSP's on-chip peripherals (such as the timer interrupt). Hardware interrupts are also differentiated by priority, which is to handle the situation where multiple hardware interrupt sources trigger interrupts at the same time. For the types and priorities of hardware interrupts, please refer to the specific chip information used.

　　If classified according to the maskable situation, interrupts can be divided into maskable interrupts (C54x supports up to 16) and non-maskable interrupts. Maskable interrupts are affected by the INTM bit in the ST1 register and the corresponding bit in the IMR register. When INTM=0, a certain bit in IMR is 1, and the corresponding interrupt is enabled. In fact, in C54x, hardware interrupts do not have to be triggered by peripheral devices. They can also be triggered by instructions INTR and TRAP, and are not restricted by INTM. One thing that needs attention is that the initialization of IPTR and peripheral circuits is different between instruction RESET reset and hardware RS reset. IPTR is always set to 0x1FF during hardware reset, and the current IPTR value will not be modified during software reset. The interrupt processing process of C54x is divided into three stages:

　　①Interrupt request. Interrupts can be requested using hardware devices or software instructions. If the requested interrupt is a maskable interrupt, the corresponding bit in the IFR register is set to 1, regardless of whether the interrupt will be serviced.

　　②Interrupt response. For software interrupts and non-maskable interrupts, the CPU responds immediately. For maskable interrupts, the following conditions must be met to respond:

　　·The highest priority (when multiple interrupts occur at the same time)

　　·The INTM bit is 0

　　·The corresponding bit in IMR is 1

　　The CPU will generate a message after fetching the first word of the software vector IACK signal, for maskable interrupts, IACK will clear the corresponding bit in IFR.

　　③Interrupt processing. Protect specific registers, execute the interrupt service routine, and restore the registers when completed. The principle of protecting registers is to correctly return and restore the environment in which the original running program was executed after executing the interrupt service routine.

　　The interrupts provided in the DSP appear in the form of an interrupt vector table (VECT) (see Table 1). The length of the interrupt vector table is 128 bytes, and each interrupt is allocated 4 bytes. There are 32 interrupts in total. The specific interrupts depend on the corresponding chip. The address of the C54x interrupt vector table is formed by the IPTR in the PMST register forming the upper 9-bit address, so the address of the vector table must be a multiple of 128. During hardware reset, IPTR is always set to 0x1FF by default, so the interrupt vector table address is 0xFF80. The address of each interrupt vector is formed as follows: PC=(IPTR)<<7+(Vector[n])<<2 (Vector[n] is the interrupt vector number, between 0 and 31), interrupt vector The number is shifted two bits to the left because each interrupt vector occupies 4 bytes. The interrupt vector table always appears in assembly form.

       2. Interrupt control in extended address mode.

　　Early DSPs had a total of 192K space (64K each for program, data and I/O spaces). As DSP processing capabilities become stronger and stronger, the 192K space can no longer meet the needs. Later C54x provided extended address mode, which expanded the program space to 8M. Interrupt control in extended mode has its own special features, which need to be explained.

　　Addressing of program space in extended mode is performed through registers PC and XPC together. PC constitutes the lower 16 address bits, and XPC constitutes the upper 7 address bits. So saving and restoring XPC is something that users must pay attention to. If the user uses the Far Call command, XPC automatically saves and restores. However, when interrupt processing is performed, only the 16-bit PC register can be automatically saved (this is due to the efficiency of interrupts in non-extended mode), so the XPC must be saved by the user himself, otherwise the XPC will often be saved when the interrupt returns. Will jump to different pages (caused by the difference in XPC values ​​before and after returning), causing unpredictable consequences. The program is shown in Table 1.

　　Since the XPC value must be saved before the long jump, delay instructions (such as FBD) cannot be used, so the interrupt latency will increase by two cycles.

　　Let’s consider another situation: Assume that the program is running on the page of )<<2, the value of XPC does not change, so the address of the interrupt vector is: 0x20000+0xPC. This clearly shows that the interrupt vector table must be in the same 64K program space page as the application. If the application is not only distributed in one program space page, how should it be handled? There are three types and a total of four techniques to deal with such a situation: (1.1) describes the situation where OVLY is arbitrary; (2.1) ~ (2.2) describes the case of OVLY=1; (3.1) describes the case of OVLY=0.

　　(1.1) In some applications, some programs are not allowed to be interrupted once they are running. Put the part of the program that does not allow interrupts into the extended space, and put the interrupt vector table and ISR as well as the part of the program that allows interrupts in the XPC=0 page. When the extended space program is called, the interrupt enable is turned off, and when the extended space program returns to the page with XPC=0, the interrupt is enabled. The advantage of this is that you don't need to pay attention to the impact of the XPC value on interrupt vector addressing. There is no need to save the XPC value when interrupting. The calling process is shown in Figure 1. Y indicates that the value of XPC needs to be paid attention to, N indicates that the value of XPC does not need to be paid attention to, and the number indicates the calling sequence.

       


(2.1) There are three factors that affect memory mapping in DSP: OVLY, DROM and MP/MC. OVLY is the abbreviation of Overlay. When OVLY=1, part of the RAM in the data space becomes an overlay area (Overlay Memory). This overlapping area is also mapped in the upper part of each page's program space. A specific example is shown in Figure 2 (MP/MC=0, C5416).

　　It can be seen that when OVLY=1, DARAM0~3 of the data space are mapped to each page of the program space. Based on such characteristics, the interrupt vector table can be positioned in the overlapping area DARAM0~3 of the data space, and OVLY is set to 1. When an interrupt occurs , no matter which program page space of the DSP the program runs in, the interrupt vector table can be correctly obtained using only PC addressing without being affected by XPC. The interrupt program ISR can be placed in any program page, but at this time Instructions to jump to the ISR can only use long jump instructions (FB, etc.). Before jumping, be sure to push the XPC into the stack. The program is the same as Table 1. The schematic diagram is shown in Figure 3.

　　(2.2) If the on-chip RAM is relatively large and the RAM allocated to the data space is relatively large (for example, C5416 has 64K of RAM that can be used as data space), there may be room for data space. At this time, you can put both the interrupt vector table and ISR into the Overlay Memory area of ​​the data space, and set OVLY to 1. In this way, not only can the interrupt vector table be correctly obtained in any program page space, but short jump instructions (BD, etc.) can be used to jump to the ISR, and there is no need to save and restore XPC. Please see Table 2 for the procedure.

　　(3.1) In extended mode, although the program space is expanded to 8M, if OVLY=1, there are a large number of overlapping areas in the program space. For example, the maximum truly available program space of C5416 is 4.03M when OVLY=1. In some cases, the program space required is greater than 4.03M, so OVLY=0 must be used. At this time, there is no overlapping area in the program space, but it can be simulated. The method is: copy the interrupt vector table to each page of program space where an interrupt will occur, as shown in Figure 4. In this way, when an interrupt occurs, the interrupt vector table can be found correctly and the interrupt jump can be realized.

　　Comparing the above four methods, method (2.1) is more suitable for common situations. It does not limit the address range of the ISR, and the interrupt vector table only occupies 0x80 space. It is easy to place it in the overlapping area of ​​the data space. The project I am working on adopts this method.

       3 Interrupt management under DSP/BIOS

　　DSP/BIOS is a quasi-real-time operating system recently launched by TI. It also supports extended address mode, but you just need to set the function calling mode in Global Settings to Far. It should be emphasized that the BIOS only supports the extended mode of OVLY=1, but not the extended mode of OVLY=0. In extended mode, there will be an extra section ".bios:.norptb" in the BIOS Code. This section will be automatically placed in the Overlay Memory. For specific reasons, please refer to Reference [4]. There are four types of threads managed by BIOS: HWI, SWI, TSK and IDL. All interrupts mentioned above belong to the HWI thread with the highest priority. Each interrupt vector exists in the form of an Object of the HWI module. You can use the Configuration Tool under the BIOS to configure the function triggered by each interrupt vector. In the Configuration Tool, you will find that there is an Object named VECT under the MEM module of the System. It is essentially used to allocate storage space to the interrupt vector table. The user can configure the address of the interrupt vector table by himself (it must be a multiple of 128 ). The address allocation method can refer to the several coping techniques mentioned above. Here are some explanations about interrupts under BIOS:

　　·When filling in the interrupt function name in the property box of the Object, if the interrupt function is written in C language, you need to add an underscore in front of the function name (C language and assembly language call each other needs). Assembly language is not required.

　　·When writing an interrupt function, you can no longer use the keyword interrupt to describe the interrupt function, because the BIOS has automatically included this function. If interrupt is used again, it will have fatal consequences.

　　·If the interrupt function is written in assembly language, the interrupt function should be sandwiched between the BIOS API HWI_enter and HWI_exit. In this way, some registers that need to be used will be correctly saved and restored during interrupt processing, and the relationship between threads and the call to the BIOS API in the interrupt function will be properly handled; if the interrupt function is written in C language, the HWI Dispatcher must be used Attributes and functions are the same as before. If you want to know more, please refer to reference [5].

　　·Under the SWI (Software Interrupt) module in the BIOS, users can add software interrupt objects themselves. However, it must be conceptually clear that the software interrupt added here is a completely different concept from the software interrupt mentioned earlier (i.e., interrupts triggered by INTR, TRAP, and RESET). The software interrupt here does not belong to the interrupt vector in the interrupt vector table (obviously there will be no limit on the number of interrupts), and it can take two parameters (the previous interrupt function cannot take parameters). So from several aspects, the software interrupt function here is more like a general function in the usual sense.

　　When you first start using DSP/BIOS, you may find it troublesome, and there are many things you need to understand. But when you become familiar with it, you will find that it can help you save a lot of time dealing with low-level things, and allow you to focus more on the implementation of the algorithm.

　　This article comprehensively introduces the interrupt mechanism of the C54x series DSP, as well as some techniques in the use of interrupts, and explains the entire interrupt response process and some more error-prone areas. I hope that through sharing, everyone can master the interrupt processing of C54x faster and better.

       Reference

1 TMS320C54x DSP Reference Set Volume 1: CPU and Peripherals. Texas Instruments, 2001.3

2 Interrupt Handing Using Extended Addressing of the TMS320C54x Family. Texas Instruments，1999.7

3 TMS320 DSP/BIOS User’s Guide. Texas Instruments，2002.11

4 DSP/BIOS and TMS320C54x Extended Addressing. Texas Instruments， 2000.11

5 TMS320C5000 DSP/BIOS Application Programming Inter-face Reference Guide. Texas Instruments，2002.10