Real-time multi-interrupt task processing of TMS320F24x

　　introduction

　　TMS320F240 integrates complete peripheral equipment, including two 10-bit A/D converters and a serial communication interface module (SCI), as well as its unique, which can provide three 16-bit timers, three single Comparison unit and event manager unit for 3 full comparison units. The F240 chip uses an interrupt structure in which multiple interrupt sources share the same interrupt level of the DSP core. Compared with commonly used mathematical control chips, it provides more interrupt sources and can meet the real-time multi-interrupt task processing requirements for complex control objects, making Users can write interrupt handlers more conveniently and flexibly.

　　1 Characteristics of TMS320F240 interrupt system and interrupt response process

　　1.1 Characteristics of the interrupt system of TMS320F240

　　The basic feature of the TMS320F240 chip interrupt system is that by giving each interrupt source a different priority, multiple interrupt sources can share the same interrupt level in the DSP core, thereby providing more interrupt sources and more flexible interrupt processing methods. Specifically, in the F240 device, all interrupt requests are sent to the DSP core for processing. For maskable interrupts, the DSP core only provides 6 maskable interrupt levels (INT1 ~ INT6). The F240 has much more than 6 maskable interrupt sources (for example: only the 3 general-purpose timers of the F240 device have 12 maskable interrupt sources, and there are as many as 36 interrupt sources available to users). Therefore, in F240, each of the six interrupt levels will be shared by multiple interrupt sources. That is, when F240 implements multiple interrupt tasks, there will basically be multiple interrupt sources sharing the same interrupt of the DSP core. When more than one hardware interrupt is triggered and suspended, F240 will execute the corresponding interrupt service subroutine in order of priority. The F240 device can identify the following 4 types of interrupt sources: ①Reset interrupt; ②External interrupt generated by 6 external pins (XINT1, XINT2, XINT3, PDPINT, RS and NMI pins); ③By on-chip peripheral modules, Including peripheral interrupts generated by the event management module (EV), A/D conversion module (ADC), serial communication module (SCI), etc.; ④ Software interrupts caused by INTR instructions, NMI instructions or TRAP instructions, etc.

　　Among them, except for software interrupts and two external hardware interrupts RS and NMI, which are non-maskable interrupts, the rest are maskable interrupts. Compared with maskable interrupts, non-maskable interrupts involve fewer registers and are simpler to handle. This article mainly conducts a detailed analysis of multi-interrupt task processing with maskable interrupts.

　　1.2 Structure of TMS320F240 multi-level interrupt register

　　In the program space of TMS320F240, the interrupt vector occupies the address space of 0000h~0003fh. The interrupt vector address is divided into two address units so that double-word transfer instructions can be stored in these units. In order to deal with the problem of multiple interrupt sources sharing the same interrupt level of the DSP core, multi-level interrupt control registers are provided internally in the DSP to meet needs. (1) CPU total interrupt level register ① Interrupt mask register (IMR). It contains mask bits used to enable or disable each interrupt level (INT1 ~ INT6). The address is 0004h. The status of each bit is shown in Figure 1. It is used to mask external and internal hardware interrupts (except NMI and RS). When a hardware interrupt is to be masked, the corresponding bit is cleared to 0; when a hardware interrupt is to be enabled, the corresponding bit is set to 1, and each bit is not affected by hardware reset. In Figure 1, 0 indicates that the number read is 0 under normal circumstances, R indicates reading, W indicates writing, and -0 indicates that the bit is 0 after reset. ②Interrupt flag register (IFR). It contains flag bits used to indicate the maskable interrupt request that has been sent to the CPU in the INT1 ~ INT6 interrupt levels. The address is 0006h. The situation is shown in Figure 2. When a maskable interrupt reaches the CPU, the corresponding flag bit of the IFR is set to 1, indicating that the corresponding interrupt (INT1~INT6) is pending or waiting for a response. Writing 1 to the corresponding flag bit clears the corresponding bit and clears its interrupt request. In Figure 2, 0 means that the number read is 0 under normal circumstances, R means reading, W1C means clearing this bit to 0 when writing 1, and -0 means this bit is set to 0 after reset. (2) Peripheral device interrupt source hierarchical control register For each specific interrupt source generated by the peripheral, the DSP provides two corresponding hierarchical control registers, including a sub-flag bit interrupt control register and a sub-mask bit interrupt control register. For interrupt events generated by the event manager, each interrupt source has a corresponding interrupt control register, as shown in Figure 3. ①Three sets of event interrupt sub-mask registers (EVIMRA/EVIMRB/EVIMRC) to mask the corresponding event manager interrupts. The meaning of EVIMRi(i=A,B,C) is basically the same as that of IMR. ②Three sets of event interrupt sub-flag registers (EVIFRA/EVIFRB/EVIFRC) to indicate the corresponding event manager interrupt. The meaning of EVIFRi(i=A,B,C) is basically the same as that of IFR. For system module interrupts, the interrupt mask bits and interrupt flag bits of each interrupt event are provided by each dedicated hierarchical module register. For example, the SCI interrupt, the masking and enabling of the sweep interrupt RXINT are set by the interrupt bit RX/BKEN of the control register SCICLT2 in the SCI module. When a receive interrupt occurs, the RXRDY bit of SCI's receive status register SCIRXST is set to 1 to indicate that a receive interrupt has occurred. Figure 4 Schematic diagram of multi-interrupt task response processing for maskable interrupts. In addition, it is worth noting that there is also an interrupt total mask bit-INTM in the ST0 status register of the DSP core. When INTM is 0, interrupts are enabled and unmaskable interrupts are allowed to be enabled; when INTM is 1, all maskable interrupts are disabled.

　　1.3 Interrupt response process of TMS320F240

　　(1) TMS320F240 interrupt response process When an interrupt event occurs, the F240 device performs interrupt processing in three stages. ①Receive interrupt request. An interrupt request is raised by a software interrupt (from program code) or hardware interrupt (from pins or on-chip peripherals), which suspends the main program. ②Response to interrupt. If the interrupt is maskable, the F240 device responds to the interrupt when the application conditions for these maskable interrupts are met; for non-maskable hardware interrupts and software interrupts, the F240 device will respond immediately.

 ③Execute the interrupt service subroutine. Once the interrupt is responded to, the F240 device transfers to its corresponding interrupt subroutine ISR (Interrupt Service Routine). F240 executes the interrupt service program written by the user according to the transfer instruction placed by the user at the predetermined address (vector storage unit). When completing real-time processing of multiple interrupt tasks, respond to interrupt sources of different levels and directly enter the corresponding ISR for processing. For multiple interrupt sources that share the same interrupt priority in the DSP core, the DSP uses the internal multi-level interrupt control register to identify the interrupt request issued by each interrupt source with multiple interrupt flags. Figure 4 is a schematic diagram of the multi-interrupt task request response processing process in which multiple interrupt sources share INT3 level interrupts. When an interrupt signal (TPINT2/TOFINT3) is received, the flag bit in the corresponding interrupt source sub-flag register (EVIFRB) is set to indicate that an interrupt has been requested. If the mask bit in the interrupt source sub-mask register (EVIMRB) is also set to enable interrupts, the signal is sent to the arbitration logic. The arbitration logic may receive similar multi-interrupt task signals from one or more interrupt control registers at the same time. . The arbitration logic compares the priorities of these competing interrupt requests and sends the interrupt with the highest priority to the CPU. The interrupt flag bit corresponding to the received interrupt priority level in the CPU's total interrupt level flag register IFR will be set, indicating that the interrupt is pending. If the corresponding mask bit in the total interrupt level mask register IMR is 1, and the DSP interrupt total mask bit INTM is 0, the CPU responds to the interrupt and executes the corresponding interrupt service subroutine. (2) Interrupt vector offset address In order to better handle the problem of multiplexing multiple interrupt sources, DSP adopts the vector offset address method. Because the interrupt flag resolution method requires multiple conditional judgments to identify the specific interrupt sources involved; while the interrupt vector offset address method only requires two instructions to complete the resolution task, reducing the memory usage of the program memory. Storage overhead saves CPU clock overhead. The DSP controller assigns a different interrupt vector offset address to each interrupt of the event management module. When an event management module sends a request signal, the vector offset address of the interrupt is automatically written into the corresponding event management interrupt vector register (EVIVRA/EVIVRB/EVIVRC). For interrupts generated by the system peripheral module, the DSP controller writes the allocated interrupt vector offset address into the system interrupt vector register (SYSIVR). The user can obtain the interrupt vector offset address of the peripheral interrupt by reading this register. Therefore, when programming and developing, you must first compile an interrupt vector table. You should also compile unused interrupts and return them to an empty position to avoid unexpected situations. Here, a schematic structural diagram of the INT3 level interrupt vector register of event manager group B is given, as listed in Table 1. For detailed information about the Interrupt Vector Register (IVR) location for each interrupt level and the offset for each interrupt event, see the F240 data sheet.

　　Table 1 TMS320F240 INT3 level interrupt control vector table Interrupt source name DSP core interrupt level vector address Peripheral vector register address Peripheral vector offset address Whether the controller module interrupt function can be masked TPINT2 INT3 (0006H) Event manager interrupt group B EVIVRB ( 7433H) 002AH Yes EV.GPT2 Timer 2 period interrupt TCINT2 002CH Yes EV.GPT2 Timer 2 comparison interrupt TUFINT2 002DH Yes EV.GPT2 Timer 2 underflow interrupt TOFINT2 002EH Yes EV.GPT2 Timer 2 overflow interrupt TPINT3 002FH Yes EV.GPT3 Timer 3 period interrupt TCINT3 0030H Available EV.GPT3 Timer 3 comparison interrupt TUFINT3 0031H Available EV.GPT3 Timer 3 underflow interrupt TOFINT3 0032H Available EV.GPT3 Timer 3 overflow interrupt

　　2 Software implementation of TMS320F240 real-time multi-interrupt task processing

　　Since the F240 device adopts an interrupt method in which multiple interrupt sources share the same interrupt level of the core, it not only provides more interrupt sources, but also allows users to easily handle interrupt requests from various interrupt sources. As shown in Figure 5, when multiple interrupt tasks are generated in the system, once an interrupt task is responded to, the CPU terminates the currently executing program code, transfers to the interrupt service subroutine, and executes it. The interrupt service subroutine is mainly completed in two steps. ① Transfer to the general interrupt service routine (GISR-G function Interrupt Service Routine). When an interrupt in the interrupt level is responded to, the CPU will transfer to the corresponding vector address and transfer to the GISR based on this address. For example, if an interrupt in INT3 is serviced, the program counter (PC) value is stored on the top of the stack, and then the PC is loaded into the program register address 0006h. Addresses 0006h and 0007h contain a branch instruction. This instruction causes the CPU to transfer to GISR. ② Transfer to the specific interrupt service routine (SISR-Special Interrupt Service Routine). When a peripheral interrupt request is serviced, the peripheral generates a vector address offset corresponding to that specific interrupt event. This offset is typically latched in the system interrupt vector register (SYSIVR) or the event management interrupt vector register (EVIVRA/EVIVRB/EVIVRC). GISR must read the value stored in IVR, determine the specific sub-interrupt source, and generate the transfer target address to the SISR accordingly, and then perform specific interrupt processing. After processing the SISR, the ISR ends with a return instruction RET. This instruction will pop the return address off the stack. The CPU then continues execution of the interrupted code sequence. If there is no sharing of multiple interrupt sources for a certain interrupt level, interrupt processing can be performed directly in GISR. At this time, there is no need to enter the SISR to determine the sub-interrupt source. In addition, after entering the interrupt, the INTM bit is automatically set to 1 to prevent other maskable interrupts. If you want to allow interrupt nesting, you need to clear the INTM bit (CLRC INTM) in the ISR and re-enable maskable interrupts globally so that the new ISR can be nested. Figure 6 Interrupt service program structure block diagram. Combined with a specific robot DSP control program, an example of DSP real-time multi-interrupt task processing is given below. In this robot DSP control program, a total of four real-time interrupt processing tasks need to be completed, and it involves multiple interrupt sources sharing the same interrupt level of the DSP core. The structure diagram of the interrupt service program is shown in Figure 6. The serial interrupt SCI occupies the first level interrupt of INT1 to complete the communication task between the DSP and the host computer. The timer T1 interrupt occupies the second level interrupt of INT2 to complete the sensor's position information collection and PID control tasks. The timer T2 interrupt and timer T3 interrupt share the INT3 third-level interrupt to complete the task of generating two PWM waveforms. The vector offset addresses of the periodic interrupts of timer T2 and timer T3 are 002BH and 002FH respectively. When there is an INT3 level interrupt request, the vector offset address of the interrupt is determined in the corresponding interrupt service routine (ISR) to determine whether a timer T2 interrupt or a timer T3 interrupt has occurred, and then transfer to timer T2 /T3 corresponding sub-interrupt service routine. In the interrupt service program, it is necessary to write interrupt protection and interrupt recovery code according to the usage of various registers in the interrupt program. That is, when entering the ISR, these register variables must be stack protected; when the ISR is completed, the These register variables undergo stack restoration. In addition, when writing an interrupt service routine, pay attention to properly processing the interrupt flag bits and interrupt mask bits of each register to prepare for the next interrupt. The following is the core code of the given robot interrupt service program, which mainly elaborates on the interrupt processing of two timer interrupt sources sharing the INT3 interrupt level. For the two interrupt tasks INT1 and INT2, since there is no problem of sharing multiple interrupt sources, interrupt processing is relatively simple, and you can directly enter the corresponding ISR. Please see the network supplement for the corresponding interrupt handler.

　　Conclusion

　　In the process of using DSP for digital control, more interrupts must be used to successfully complete the control tasks of complex control systems. F240 is a typical representative of the DSP TMS320F24x series. Mastering the interrupt processing method of F240 is also of reference significance for TMS320F241/F243/C242 and TMS320LF2406/LF2407 chips of the TMS320F24x series. Therefore, this processing method also has certain versatility. The author applies this processing method to the software development of the master-slave remote control robot control system based on TMS320F240. Practice has proven that this can meet the requirements of real-time multi-interrupt task processing for robots and achieve good practical results.