Interrupt Mechanism of TMS320C54x Series DSP

1 Interrupt mechanism in C54x

The interrupt signal is essentially a signal driven by hardware or software, which can cause the DSP to pause the executing program and enter the interrupt service routine (ISR). In the most typical DSP system, if the A/D converter needs to send data to the DSP, or the D/A converter needs to take data from the DSP, a request is sent to the DSP through a hardware interrupt.

The C54x series DSP supports software interrupts and hardware interrupts. Software interrupts are triggered by instructions (INTR, TRAP, RESET), and hardware interrupts are triggered by peripheral devices. Hardware interrupts are actually divided into two categories: one is triggered by DSP's off-chip peripherals (such as A/D converters), and the other is triggered by DSP's on-chip peripherals (such as timer interrupts). Hardware interrupts are also prioritized to handle situations where multiple hardware interrupt sources trigger interrupts at the same time. For the types and priorities of hardware interrupts, please refer to the specific chip information used.

If classified according to the maskability, interrupts can be divided into maskable interrupts (C54x supports up to 16 interrupts) and non-maskable interrupts. Maskable interrupts are affected by the INTM bit in the ST1 register and the corresponding bit in the IMR register. When INTM=0, a bit in IMR is 1, then the corresponding interrupt is open. In fact, in C54x, hardware interrupts do not have to be triggered by peripheral devices. They can also be triggered by instructions INTR and TRAP, and are not restricted by INTM. One thing that needs to be noted is that the initialization of IPTR and peripheral circuits by instruction RESET and hardware RS reset is different. IPTR is always set to 0x1FF during hardware reset, and the current IPTR value will not be modified during software reset. The interrupt processing process of C54x is divided into three stages:

① Interrupt request. An interrupt can be requested by a hardware device or software instruction. If the requested interrupt is a maskable interrupt, the corresponding bit in the IFR register is set to 1, regardless of whether the interrupt will be responded to.

②Interrupt response. For software interrupts and non-maskable interrupts, the CPU responds immediately. For maskable interrupts, the following conditions must be met before responding:

Highest priority (when multiple interrupts occur at the same time)

INTM bit is 0

The corresponding bit in IMR is 1

The CPU will generate an IACK signal after fetching the first word of the software vector. For maskable interrupts, IACK will clear the corresponding bit in IFR.

③Interrupt processing. Protect specific registers, execute the interrupt service program, and restore the registers after completion. The principle of protecting registers is to correctly return and restore the original running program environment after executing the interrupt service program.

The interrupts provided in DSP appear in the form of interrupt vector table (VECT) (see Table 1). The length of the interrupt vector table is 128 bytes, and each interrupt is allocated 4 bytes. There are 32 interrupts in total. The specific interrupt depends on the corresponding chip. The address of the C54x interrupt vector table is formed by the high 9-bit address of IPTR in the PMST register, so the address of the vector table must be a multiple of 128. When the hardware is reset, IPTR is always set to 0x1FF by default, so the address of the interrupt vector table is 0xFF80. The address of each interrupt vector is formed as follows: PC=(IPTR)<<7+(Vector[n])<<2 (Vector[n] is the interrupt vector number, between 0 and 31). The interrupt vector number is shifted left by two bits because each interrupt vector occupies 4 bytes. The interrupt vector table always appears in assembly form.

2 Interrupt control in extended address mode

Early DSPs had a total of 192K of space (64K each for program, data, and I/O). As DSP processing power became stronger, 192K of space could no longer meet the needs. Later C54x provided an extended address mode, which expanded the program space to 8M. The interrupt control in the extended mode has its own special features, which need to be explained.

In extended mode, the addressing of program space is done through registers PC and XPC. PC constitutes the lower 16-bit address bits, and XPC constitutes the upper 7-bit address bits. Therefore, users must pay attention to saving and restoring XPC. If the user uses the Far Call instruction, XPC will be automatically saved and restored. However, when interrupt processing is performed, only the 16-bit PC register can be automatically saved (this is due to the efficiency of interrupts in non-extended mode), so XPC must be saved by the user himself, otherwise it will often jump to different pages when the interrupt returns (caused by the different XPC values ​​before and after the return), resulting in unpredictable consequences. The program is shown in Table 1.

Since the value of XPC must be saved before the long jump, delay instructions (such as FBD) cannot be used, so the interrupt latency will increase by two cycles.

Let's consider another case: suppose the program is running on the page with XPC=2. If an interrupt occurs and gets a response from the CPU, the DSP will load the PC: PC=(IPTR)<<7+(Vector[n])<<2, and the value of XPC does not change, so the address of the interrupt vector is: 0x20000+0xPC. This clearly shows that the interrupt vector table must be in the same 64K program space page as the application. If the application is not distributed in only one program space page, how should it be handled? There are three types and four techniques to deal with such a situation: (1.1) describes the situation where OVLY is arbitrary; (2.1) to (2.2) describe the situation where OVLY=1; (3.1) describes the situation where OVLY=0.

(1.1) In some applications, some programs are not allowed to be interrupted once they are running. Put the program part that does not allow interrupts in the extended space, and put the interrupt vector table, ISR and the program part that allows interrupts in the page with XPC=0. Turn off the interrupt enable when calling the program in the extended space, and turn on the interrupt again when the extended space program returns to the page with XPC=0. The advantage of doing this is that you do not need to pay attention to the impact of the XPC value on the interrupt vector addressing. There is no need to save the XPC value when interrupting. The calling process is shown in Figure 1, Y means that you need to pay attention to the XPC value, N means that you do not need to pay attention to the XPC value, and the number indicates the calling order.

(2.1) There are three factors that affect memory mapping in DSP: OVLY, DROM and MP/MC. OVLY is the abbreviation of Overlay. When OVLY=1, a part of the RAM in the data space becomes the overlap area (Overlay Memory). This overlap area is mapped at the top of each page of program space. A specific example is shown in Figure 2 (MP/MC=0, C5416).

It can be seen that when OVLY=1, DARAM0~3 of the data space are mapped to each page of the program space. Based on this feature, the interrupt vector table can be located in the overlapping area DARAM0~3 of the data space, and OVLY can be set to 1. When an interrupt occurs, no matter which program page space of the DSP the program runs in, the interrupt vector table can be correctly obtained by only using PC addressing without being affected by XPC. The interrupt program ISR can be placed in any program page, but at this time, the instruction to jump to the ISR can only use a long jump instruction (FB, etc.). Before jumping, pay attention to pushing XPC into the stack. The program is the same as Table 1. The schematic diagram is shown in Figure 3.

(2.2) If the on-chip RAM is relatively large, and the RAM allocated to the data space is relatively large (e.g., C5416 has 64K RAM that can be used as data space), there may be some margin in the data space. At this time, the interrupt vector table and ISR can all be placed in the Overlay Memory area of ​​the data space, and OVLY can be set to 1. In this way, not only can the interrupt vector table be correctly obtained in any program page space, but also a short jump instruction (BD, etc.) can be used to jump to the ISR, and there is no need to save and restore the XPC. Please refer to Table 2 for the program.

(3.1) In extended mode, although the program space is expanded to 8M, if OVLY=1, there will be a large number of overlapping areas in the program space. For example, the maximum available program space for C5416 when OVLY=1 is 4.03M. In some cases, the required program space is larger than 4.03M, so OVLY=0 must be used. At this time, there is no overlapping area in the program space, but it can be simulated. The method is: copy the interrupt vector table to each page of the program space where an interrupt will occur, as shown in Figure 4. In this way, the interrupt vector table can be correctly found when an interrupt occurs, and the interrupt jump can be realized.

Compared with the above four methods, method (2.1) is more suitable for general situations. It does not limit the address range of the ISR, and the interrupt vector table only occupies the space of 0x80. It is easy to put it in the overlapping area of ​​the data space. The project I am working on adopts this method.

3 Interrupt Management under DSP/BIOS

DSP/BIOS is a quasi-real-time operating system recently launched by TI. It also supports extended address mode. You just need to set the function call mode in Global Settings to Far. It should be emphasized that BIOS only supports extended mode with OVLY=1, but not with OVLY=0. In extended mode, there will be an extra segment ".bios:.norptb" in the BIOS Code. This segment will be automatically placed in Overlay Memory. For specific reasons, please refer to the references. There are four types of threads managed by BIOS: HWI, SWI, TSK and IDL. All the interrupts mentioned above belong to the HWI thread with the highest priority. Each interrupt vector exists in the form of an object of the HWI module. The Configuration Tool under BIOS can be used to configure the function triggered by each interrupt vector. In the Configuration Tool, you will find an object named VECT under the MEM module of System. It is actually used to allocate storage space for the interrupt vector table. The user can configure the address of the interrupt vector table by himself (it must be a multiple of 128). The address allocation method can refer to the several coping techniques mentioned above. Here are a few explanations about interrupts under BIOS:

When filling in the interrupt function name in the Object property box, if the interrupt function is written in C language, you need to add an underscore before the function name (necessary for C language and assembly language to call each other). Assembly language does not need it.

When writing an interrupt function, you can no longer use the keyword interrupt to describe the interrupt function, because the BIOS has automatically included this function. If you use interrupt again, it will cause fatal consequences.

If the interrupt function is written in assembly language, it should be placed between the BIOS API HWI_enter and HWI_exit. In this way, some registers that need to be used will be correctly saved and restored during interrupt processing, and the relationship between threads and the call to the BIOS API in the interrupt function will be properly handled; if the interrupt function is written in C language, the HWI Dispatcher attribute must be used, and the function is the same as before. If you want to know more, please refer to the references.

In the SWI (software interrupt) module in the BIOS, users can add software interrupt objects themselves. However, it must be clearly understood that the software interrupt added here is completely different from the software interrupt mentioned above (i.e., the interrupt triggered by INTR, TRAP, and RESET). The software interrupt here does not belong to the interrupt vector in the interrupt vector table (obviously, there is no limit on the number of interrupts), and it can take two parameters (the previous interrupt function cannot take parameters). So from several aspects, the software interrupt function here is more like a general function in the usual sense.

When you first start using DSP/BIOS, you may find it troublesome and there are many things you need to understand. But when you become familiar with it, you will find that it can help you save a lot of time dealing with low-level things, and let you focus more on the implementation of the algorithm.

This article comprehensively introduces the interrupt mechanism of the C54x series DSP, as well as some tips on using interrupts, and explains the entire interrupt response process and some places where errors are prone to occur. I hope that through sharing, everyone can master the interrupt processing of C54x faster and better.