Low power 24-bit analog-to-digital converter AD7787
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1 Overview AD7787 is a low-power, low-noise, dual-channel, 24-bit Σ-Δ analog-to-digital converter launched by ADI for low-frequency measurement. It uses the on-chip clock circuit to work, so there is no need for the user to provide a clock source. The data output rate of AD7787 can be set by software, and this feature allows its conversion rate to vary between 9.5Hz and 120Hz. The chip uses a 10-pin MSOP package and is very suitable for portable instruments, temperature measurements, sensor measurements, weighing instruments, etc. that require high resolution and low power consumption. The main features of AD7787 are as follows: ●Can operate in the voltage range of 2.5V to 5.25V. The maximum operating current is 75μA in normal mode and 1μA in power-down mode; 1.1μV RMS noise at 9.5Hz slew rate 19.5-bit peak-to-peak resolution at 22-bit effective resolution ●Internal nonlinearity: 3.5ppm; ●With 50Hz and 60Hz synchronous suppression function; ●With internal clock oscillator and VDD monitoring channel; ●Built-in rail-to-rail input buffer; ●With three-wire serial interface, compatible with SPI, QSPI, MICROWIRE and DSP; ●The operating temperature range is -40～+105℃.
2 Pin Arrangement and Function The pin arrangement of AD7787 is shown in Figure 1. 3 Working Principle The internal structure and function block diagram of AD7787 is shown in Figure 2. It integrates a Σ-Δ modulator, a buffer and an on-chip digital filter. The main function of the digital filter is to provide normal mode rejection. Under the default conversion rate of 16.6Hz, it can provide synchronous rejection of 50Hz and 60Hz. AD7787 works with an internal clock circuit, so no external clock source is required. The clock frequency is divided by 2, 4, and 8 factors and applied to the modulator and filter, which can reduce the power consumption of the chip. When powered by a single 5V power supply, the buffer is enabled and the clock is working at the maximum rate, the maximum power consumption current of AD7787 is only 160μA. AD7787 has 5 on-chip registers: communication register, status register, mode register, filter register and data register. All settings and controls of AD7787 are realized through these registers. AD7787 has three working modes: single conversion mode, continuous conversion mode and continuous mode.
3.1 Single Conversion Mode The conversion timing in single conversion mode is shown in Figure 3. In this mode, the AD7787 is placed in shutdown mode during the conversion. Single conversion can be initialized by setting the MD1 bit of the mode register to 1 and the MD0 bit to 0. After power-on, the AD7787 first performs single conversion mode and then returns to shutdown mode. This conversion requires 2 ADC clock cycles. After the conversion is completed, DOUT/RDY goes low. After the data word is read out from the data register, DOUT/RDY goes high. If CS is low, DOUT/RDY will remain high until another conversion is initiated and completed. In fact, if necessary, the data register can still be read several times even if DOUT/RDY has become high. 3.2 Continuous Conversion Mode Figure 4 shows the timing for the continuous conversion mode. This is the power-up default mode. When the AD7787 is performing continuous conversions, the RDY pin in the status register goes low after each conversion. If CS is low, the DOUT/RDY line will also go low after the conversion is complete. The user can indicate that the next operation is to read the data register by writing to the communications register. Once the SCLK pulse is applied to the ADC, the digital conversion is placed on the DOUT/RDY pin. When the conversion is read, DOUT/RDY will return to a high level. The user can read the register several more times if necessary, but must ensure that the data register is not accessed before the next conversion is complete, otherwise the new conversion word will be lost. 3.3 Continuous Read Mode The conversion timing in continuous read mode is shown in Figure 5. In this mode, after the user writes 001111XX to the communication register, the system only needs to provide the appropriate number of SCLK cycles to the ADC and the system will automatically place the 24-bit word on the DOUT/RDY line after the conversion is completed. This is more advanced than writing to the communication register after each conversion is completed to access the data. In fact, when DOUT/RDY goes low to indicate the end of conversion, the system must provide enough SCLK cycles to the ADC and put the data conversion on the DOUT/RDY line at the same time. When the conversion result is read out, DOUT/RDY returns to a high level until the next conversion starts. In this mode, the user can only read the data and must ensure that the data word is read out before the end of the next conversion. If the user does not read the data before the end of the next conversion, or the AD7787 does not have enough time to read it, the serial output register will be reset at the end of the next conversion and save the new conversion result. The continuous read mode can be exited by writing the 001110XX instruction to the communication register when the RDY pin goes low. In the continuous read mode, if the ADC monitor is activated on the DIN line, it will receive a command to exit the continuous read mode. In addition, if 32 consecutive 1s appear on the DIN line, the ADC is reset and DIN remains low until the instruction is written to the chip again. 4 Issues that need attention in application 4.1 Analog Input Channels The absolute input voltage range of the AD7787 in buffered mode is limited to GND+100mV~VDD-100mV, so the common-mode voltage must be set carefully to avoid exceeding the limit and reducing the linearity and noise performance of the AD7787; the absolute input voltage range in unbuffered mode is GND-100mV~VDD+30mV, and small true bipolar signals relative to ground cannot be monitored at this time. It should also be noted that since the unbuffered input channel provides a dynamic load to the driving source. Therefore, the resistor/capacitor connected to the input pin will cause a DC gain error, the size of which depends on the output impedance of the driving ADC input source.
Figures 3, 4, 5 4.2 Reference input
When applying the reference input, care should be taken because the reference input may present a high impedance dynamic load. Therefore, the resistor/capacitor connected to the input pin may also cause a DC gain error, the magnitude of which depends on the output impedance of the source driving the reference input. In addition, since the output impedance of the recommended reference voltage source is low, a decoupling capacitor should be connected to the REFIN pin, and the principle should be that no gain error is introduced into the system. The reference input voltage obtained through an external resistor means that the reference input can be seen as a large external source impedance, so external decoupling devices on the REFIN pin are not recommended for this type of circuit configuration. 4.3 Grounding and wiring The AD7787 is more immune to noise interference than traditional high-resolution converters. Its digital filter suppresses broadband noise on the power supply voltage and removes noise from the analog input and reference input. However, because the AD7787 has high resolution and generates very low noise, ground and wiring must be properly designed. When designing the AD7787 printed circuit board, the analog and digital parts should be separated and confined to a certain area within the board. At the same time, the GND pin of the AD7787 should be connected to the AGND of the system. In any wiring layer, the user must pay attention to the current flow within the system to ensure that the return path of all currents is as close as possible to the path they take to reach their destination to avoid digital currents flowing through the AGND part of the board. To prevent noise coupling, a ground line should be laid under the layer where the AD7787 is located. In addition, to reduce the impedance and interference effect on the power line, the power line of the AD7787 should be widened as much as possible. Fast conversion signals (such as clock signals) must be shielded with digital ground to prevent them from radiating noise to other parts of the board. In addition, mutual interference between digital and analog signals should be avoided. Do not route the traces on different adjacent layers at right angles to avoid feedthrough noise. When using high-resolution ADCs, the decoupling design of power supply and ground is crucial. For this reason, the power supply VDD should use capacitor bypass technology, use 0.1μF bypass capacitors and connect the corresponding power supplies and ground with the shortest possible path, so that high-frequency components can be bypassed. At the same time, a 10μF tantalum capacitor should be connected in parallel to bypass low-frequency components. All logic chips should be decoupled through 0.1μF ceramic capacitors.
5 Application Circuit In battery monitoring, it is usually necessary to measure the battery current and voltage. The specific monitoring circuit is shown in Figure 6. In the figure, the current flows through a 100μΩ resistor, and its value varies between -200A and +2000A. The measurement of this current can be achieved by directly connecting the AIN1 channel to the shunt resistor. The battery voltage ranges from 12V to 42V, with a peak voltage of 60V. Before it is applied to the AD7787, this voltage can be attenuated using an external resistor network. Since the AD7787 itself has a buffer, the user can directly connect the AIN2 channel to the high-impedance attenuator circuit without worrying about introducing gain errors.
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