A design of a 10Base-T standard interface amplifier circuit

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A design of a 10Base-T standard interface amplifier circuit [Copy link]

A design of a 10Base-T standard interface amplifier circuit

Chen Zhiwei, Cai Min (School of Physical Science and Technology, South China University of Technology, Guangzhou 510640)

1 Introduction 10Base-T is the Ethernet physical layer standard adopted by IEEE in 1990. Its position in the OSI (Open Systems Interconnection) network protocol standard is shown in Figure 1[1]. Ethernet has now developed into 10000Base-X Ethernet based on the IEEE802.3ae standard [2]. This paper proposes the design of a 10Base-T amplifier circuit mainly because many terminal network devices currently use 10Base-T interfaces, and its own technical characteristics (such as coding characteristics) and performance stability make it a good choice in some systems that require low transmission rates but high working stability. In the 10Base-T standard, two types of Manchester-coded differential signals with a phase difference of 180 degrees are transmitted on the twisted pair (in the actual transmission process, the transmitter performs pre-distortion processing on the Manchester code to eliminate inter-code interference, so the transmitted signal is different from the ideal Manchester code) [3]. In the local area network system, the data signal is transmitted in the form of a rectangular wave, which is characterized by fast attenuation, susceptibility to interference, and baseband drift when the signal passes through the coupling transformer [4]. Therefore, the transmitted signal must be amplified and shaped in the 10Base-T device interface. The preamplifier designed in this paper is used to process the signal transmitted by the twisted pair cable. It has the functions of reducing noise interference, overall signal waveform, amplifying the transmitted signal and converting the analog signal into a digital signal. No additional filters and A/D converters are required. In addition, a large number of repeated modules are used in the circuit design to improve the reliability of the circuit. At the same time, the 0.5μm COMS process of the previous circuit with the same function is improved to 0.25μm COMS process, which reduces the chip power consumption and occupied area. 2 Overall Structure Based on the type and characteristics of the transmission signal, the corresponding interface circuit is designed. The circuit consists of P-end and N-end input ports, R1 and R2 resistor network modules, Z1 to Z14 signal shaping and amplification modules, S1 bias module, Buffer1 and buffer2 buffer modules. The circuit structure block diagram is shown in Figure 2. The two differential signals sent from the twisted pair cable enter the R1 and R2 modules from the P and N terminals respectively. After simple processing, they are changed into 8 pairs of differential signals and sent to the shaping and amplification modules. After the first stage of shaping and amplification, the signals generate 4 pairs of differential signals and send them to the second stage of shaping and amplification modules. The generated 2 pairs of differential signals are then sent to the third stage of shaping and amplification modules and output through 2 buffer modules. 3 Module Design 3.1 Resistor Network Module The specific circuit design of the resistor network module is shown in Figure 3. The front part of the circuit is a resistor network, in which R1-R8 are resistors with equal resistance and the same characteristics, which are used to increase the input impedance. Finally, the two positive and negative signals are divided into four paths and enter the amplification and shaping module. The two resistors R4 and R8 are connected to the power supply and ground respectively, which are used to increase the difference in DC level between the P terminal and the N terminal (Figure 4). From the figure, we can see that the above resistors pull up and pull down, making the differential voltage of the two differential signals larger, which will be beneficial to the subsequent work of the amplification and shaping module. 3.2 Amplification and Shaping Module The specific circuit design of the amplification and shaping module is shown in Figure 5. Since the signals coming from the input end are all high-level or low-level differential signals, the design of the amplifier circuit mainly adopts mirror differential [5]. The large signal analysis of the amplifier shaping module circuit is performed. Here, it is assumed that M5 is an ideal current source. If a low-level signal is input at the Vin1 end and a high-level signal is input at the Vin2 end, the M1 tube is turned off, and M3 and M4 are also turned off. At this time, the path from the power supply to the ground is turned off, and no current flows between the power supply and the ground. The M2 and M5 tubes work in the deep linear region, and the transmission current is zero. Therefore, Vout has the same potential as the ground. When the Vin1 terminal inputs a high level and the Vin2 terminal inputs a low level, the M2 tube is turned off, the current flowing through the M4 tube is zero, and the M4 tube works in the deep linear region, so Vout is at the same potential as the power supply terminal. Since in the state of high and low level conversion of the two signals, there is a state where the potential of Vin1 is the same as the potential of Vin2. Assuming that the circuits on both sides are symmetrical and the parameters of the MOS tubes are symmetrical, the current flowing through the M1 tube and the current flowing through the M2 tube are the same, both equal to half of the current flowing through the M5 tube, so Vout = Vdd-|Vgs3| = Vdd-|Vgs4|[6]. The design of the amplifier introduces M6 and M7 between the power supply and the ground, and introduces M8 between Vb and the ground. M6, M7, and M8 are all connected in the form of capacitors. It is mainly used to reduce the interference of the power supply noise on the amplified signal and enhance the stability of the circuit. In summary, ideally, the output swing of the amplifier is between the ground potential and the power supply potential. In reality, it is difficult for the circuit to be completely symmetrical, so even when a fully differential signal is input, Vout will fluctuate greatly. However, because the signal in the 10Base-T standard is a large signal with high and low levels, the slight asymmetry can be ignored to a certain extent. 3.3 Bias Module The specific circuit design of the bias module is shown in Figure 6. In Figure 2, it can be seen that each differential amplifier has a three-terminal input and a single-ended output, where the input of S1 is connected to each amplifier, and its main function is to provide a bias voltage for the amplified tail current source. As can be seen from Figure 6, two parallel diode-connected NMOS tubes are grounded to provide a bias voltage for the M5 tail current source in Figure 5. Using a single replica circuit to provide a bias voltage can ensure that the bias voltage of each amplifier is the same and reduce the occupied area when the chip is implemented. 3.4 Buffer module The specific circuit design of the buffer module is shown in Figure 7. The signal that has been amplified and shaped by the two poles still has the characteristics of an analog signal. After the buffer simulation, the signal is further filtered and completely converted into a digital signal. 4 Layout Design and Simulation Results Since the layout of the entire circuit is relatively large and there are many repeated units, only the core part of the circuit, that is, the layout design of the amplification and shaping module, is shown here (Figure 8). The entire circuit is mostly analog circuits. The circuit netlist and circuit layout are combined during simulation, and the software of Synopsys is used to verify based on the Hspice model. The excitation signal simulates the differential signal transmitted in the twisted pair and is interfered by the noise signal. The specific excitation signal is shown in Figure 9. The excitation signal enters through the P terminal and the N terminal, and the output port obtains the signal shown in 10.

This article is excerpted from "Semiconductor Technology"